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git01.mediatek.com / filogic / uboot / 6b927b17bd28ebeecd5ecf487f0035783c095824 / . / arch / xtensa / include / asm / arch-dc232b / tie-asm.h
blob: 05ce1107f5a3d008189ee70ed99669801b987cdd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Chris Zankel20efd8c2016-08-10 18:36:45 +0300[diff] [blame]2/*
3 * This header file contains assembly-language definitions (assembly
4 * macros, etc.) for this specific Xtensa processor's TIE extensions
5 * and options. It is customized to this Xtensa processor configuration.
6 * This file is autogenerated, please do not edit.
7 *
8 * Copyright (C) 1999-2007 Tensilica Inc.
Chris Zankel20efd8c2016-08-10 18:36:45 +0300[diff] [blame]9 */
10
11#ifndef _XTENSA_CORE_TIE_ASM_H
12#define _XTENSA_CORE_TIE_ASM_H
13
14/* Selection parameter values for save-area save/restore macros: */
15/* Option vs. TIE: */
16#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
17#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
18/* Whether used automatically by compiler: */
19#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
20#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
21/* ABI handling across function calls: */
22#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
23#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
24#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
25/* Misc */
26#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
27
28
29
30/* Macro to save all non-coprocessor (extra) custom TIE and optional state
31 * (not including zero-overhead loop registers).
32 * Save area ptr (clobbered): ptr (1 byte aligned)
33 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
34 */
35 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
36 xchal_sa_start \continue, \ofs
37 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
38 xchal_sa_align \ptr, 0, 1024-8, 4, 4
39 rsr \at1, ACCLO // MAC16 accumulator
40 rsr \at2, ACCHI
41 s32i \at1, \ptr, .Lxchal_ofs_ + 0
42 s32i \at2, \ptr, .Lxchal_ofs_ + 4
43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
44 .endif
45 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
46 xchal_sa_align \ptr, 0, 1024-16, 4, 4
47 rsr \at1, M0 // MAC16 registers
48 rsr \at2, M1
49 s32i \at1, \ptr, .Lxchal_ofs_ + 0
50 s32i \at2, \ptr, .Lxchal_ofs_ + 4
51 rsr \at1, M2
52 rsr \at2, M3
53 s32i \at1, \ptr, .Lxchal_ofs_ + 8
54 s32i \at2, \ptr, .Lxchal_ofs_ + 12
55 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
56 .endif
57 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
58 xchal_sa_align \ptr, 0, 1024-4, 4, 4
59 rsr \at1, SCOMPARE1 // conditional store option
60 s32i \at1, \ptr, .Lxchal_ofs_ + 0
61 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
62 .endif
63 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
64 xchal_sa_align \ptr, 0, 1024-4, 4, 4
65 rur \at1, THREADPTR // threadptr option
66 s32i \at1, \ptr, .Lxchal_ofs_ + 0
67 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
68 .endif
69 .endm // xchal_ncp_store
70
71/* Macro to save all non-coprocessor (extra) custom TIE and optional state
72 * (not including zero-overhead loop registers).
73 * Save area ptr (clobbered): ptr (1 byte aligned)
74 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
75 */
76 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
77 xchal_sa_start \continue, \ofs
78 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
79 xchal_sa_align \ptr, 0, 1024-8, 4, 4
80 l32i \at1, \ptr, .Lxchal_ofs_ + 0
81 l32i \at2, \ptr, .Lxchal_ofs_ + 4
82 wsr \at1, ACCLO // MAC16 accumulator
83 wsr \at2, ACCHI
84 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
85 .endif
86 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
87 xchal_sa_align \ptr, 0, 1024-16, 4, 4
88 l32i \at1, \ptr, .Lxchal_ofs_ + 0
89 l32i \at2, \ptr, .Lxchal_ofs_ + 4
90 wsr \at1, M0 // MAC16 registers
91 wsr \at2, M1
92 l32i \at1, \ptr, .Lxchal_ofs_ + 8
93 l32i \at2, \ptr, .Lxchal_ofs_ + 12
94 wsr \at1, M2
95 wsr \at2, M3
96 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
97 .endif
98 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
99 xchal_sa_align \ptr, 0, 1024-4, 4, 4
100 l32i \at1, \ptr, .Lxchal_ofs_ + 0
101 wsr \at1, SCOMPARE1 // conditional store option
102 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
103 .endif
104 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
105 xchal_sa_align \ptr, 0, 1024-4, 4, 4
106 l32i \at1, \ptr, .Lxchal_ofs_ + 0
107 wur \at1, THREADPTR // threadptr option
108 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
109 .endif
110 .endm // xchal_ncp_load
111
112
113
114#define XCHAL_NCP_NUM_ATMPS 2
115
116
117#define XCHAL_SA_NUM_ATMPS 2
118
119#endif /*_XTENSA_CORE_TIE_ASM_H*/
120