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git01.mediatek.com / filogic / uboot / 6b642aca7f571e777924f50732f530fd94b03bfb / . / src / arm64 / qcom / sm8350-hdk.dts
blob: 895adce59e758c3a810f37d703ff71da30d0a3db [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020-2021, Linaro Limited
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9#include "sm8350.dtsi"
10#include "pm8350.dtsi"
11#include "pm8350b.dtsi"
12#include "pm8350c.dtsi"
13#include "pmk8350.dtsi"
14#include "pmr735a.dtsi"
15#include "pmr735b.dtsi"
16
17/ {
18 model = "Qualcomm Technologies, Inc. SM8350 HDK";
19 compatible = "qcom,sm8350-hdk", "qcom,sm8350";
20 chassis-type = "embedded";
21
22 aliases {
23 serial0 = &uart2;
24 };
25
26 chosen {
27 stdout-path = "serial0:115200n8";
28 };
29
30 hdmi-connector {
31 compatible = "hdmi-connector";
32 type = "a";
33
34 port {
35 hdmi_con: endpoint {
36 remote-endpoint = <&lt9611_out>;
37 };
38 };
39 };
40
41 pmic-glink {
42 compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink";
43 #address-cells = <1>;
44 #size-cells = <0>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]45 orientation-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]46
47 connector@0 {
48 compatible = "usb-c-connector";
49 reg = <0>;
50 power-role = "dual";
51 data-role = "dual";
52
53 ports {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 port@0 {
58 reg = <0>;
59
60 pmic_glink_hs_in: endpoint {
61 remote-endpoint = <&usb_1_dwc3_hs>;
62 };
63 };
64
65 port@1 {
66 reg = <1>;
67
68 pmic_glink_ss_in: endpoint {
69 remote-endpoint = <&usb_1_qmpphy_out>;
70 };
71 };
72
73 port@2 {
74 reg = <2>;
75
76 pmic_glink_sbu: endpoint {
77 remote-endpoint = <&fsa4480_sbu_mux>;
78 };
79 };
80 };
81 };
82 };
83
84 vph_pwr: vph-pwr-regulator {
85 compatible = "regulator-fixed";
86 regulator-name = "vph_pwr";
87 regulator-min-microvolt = <3700000>;
88 regulator-max-microvolt = <3700000>;
89
90 regulator-always-on;
91 regulator-boot-on;
92 };
93
94 lt9611_1v2: lt9611-1v2-regulator {
95 compatible = "regulator-fixed";
96 regulator-name = "LT9611_1V2";
97
98 vin-supply = <&vph_pwr>;
99 regulator-min-microvolt = <1200000>;
100 regulator-max-microvolt = <1200000>;
101 gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
102 enable-active-high;
103 regulator-boot-on;
104 };
105
106 lt9611_3v3: lt9611-3v3-regulator {
107 compatible = "regulator-fixed";
108 regulator-name = "LT9611_3V3";
109
110 vin-supply = <&vreg_bob>;
111 gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
112 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>;
114 enable-active-high;
115 regulator-boot-on;
116 regulator-always-on;
117 };
118};
119
120&adsp {
121 status = "okay";
122 firmware-name = "qcom/sm8350/adsp.mbn";
123};
124
125&apps_rsc {
126 regulators-0 {
127 compatible = "qcom,pm8350-rpmh-regulators";
128 qcom,pmic-id = "b";
129
130 vdd-s1-supply = <&vph_pwr>;
131 vdd-s2-supply = <&vph_pwr>;
132 vdd-s3-supply = <&vph_pwr>;
133 vdd-s4-supply = <&vph_pwr>;
134 vdd-s5-supply = <&vph_pwr>;
135 vdd-s6-supply = <&vph_pwr>;
136 vdd-s7-supply = <&vph_pwr>;
137 vdd-s8-supply = <&vph_pwr>;
138 vdd-s9-supply = <&vph_pwr>;
139 vdd-s10-supply = <&vph_pwr>;
140 vdd-s11-supply = <&vph_pwr>;
141 vdd-s12-supply = <&vph_pwr>;
142
143 vdd-l1-l4-supply = <&vreg_s11b_0p95>;
144 vdd-l2-l7-supply = <&vreg_bob>;
145 vdd-l3-l5-supply = <&vreg_bob>;
146 vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>;
147
148 vreg_s10b_1p8: smps10 {
149 regulator-name = "vreg_s10b_1p8";
150 regulator-min-microvolt = <1800000>;
151 regulator-max-microvolt = <1800000>;
152 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
153 };
154
155 vreg_s11b_0p95: smps11 {
156 regulator-name = "vreg_s11b_0p95";
157 regulator-min-microvolt = <952000>;
158 regulator-max-microvolt = <952000>;
159 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
160 };
161
162 vreg_s12b_1p25: smps12 {
163 regulator-name = "vreg_s12b_1p25";
164 regulator-min-microvolt = <1256000>;
165 regulator-max-microvolt = <1256000>;
166 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
167 };
168
169 vreg_l1b_0p88: ldo1 {
170 regulator-name = "vreg_l1b_0p88";
171 regulator-min-microvolt = <912000>;
172 regulator-max-microvolt = <920000>;
173 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
174 };
175
176 vreg_l2b_3p07: ldo2 {
177 regulator-name = "vreg_l2b_3p07";
178 regulator-min-microvolt = <3072000>;
179 regulator-max-microvolt = <3072000>;
180 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
181 };
182
183 vreg_l3b_0p9: ldo3 {
184 regulator-name = "vreg_l3b_0p9";
185 regulator-min-microvolt = <904000>;
186 regulator-max-microvolt = <904000>;
187 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
188 };
189
190 vreg_l5b_0p88: ldo5 {
191 regulator-name = "vreg_l5b_0p88";
192 regulator-min-microvolt = <880000>;
193 regulator-max-microvolt = <888000>;
194 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
195 regulator-allow-set-load;
196 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
197 RPMH_REGULATOR_MODE_HPM>;
198 };
199
200 vreg_l6b_1p2: ldo6 {
201 regulator-name = "vreg_l6b_1p2";
202 regulator-min-microvolt = <1200000>;
203 regulator-max-microvolt = <1208000>;
204 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
205 regulator-allow-set-load;
206 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
207 RPMH_REGULATOR_MODE_HPM>;
208 };
209
210 vreg_l7b_2p96: ldo7 {
211 regulator-name = "vreg_l7b_2p96";
212 regulator-min-microvolt = <2504000>;
213 regulator-max-microvolt = <2504000>;
214 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
215 regulator-allow-set-load;
216 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
217 RPMH_REGULATOR_MODE_HPM>;
218 };
219
220 vreg_l9b_1p2: ldo9 {
221 regulator-name = "vreg_l9b_1p2";
222 regulator-min-microvolt = <1200000>;
223 regulator-max-microvolt = <1200000>;
224 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
225 regulator-allow-set-load;
226 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
227 RPMH_REGULATOR_MODE_HPM>;
228 };
229 };
230
231 regulators-1 {
232 compatible = "qcom,pm8350c-rpmh-regulators";
233 qcom,pmic-id = "c";
234
235 vdd-s1-supply = <&vph_pwr>;
236 vdd-s2-supply = <&vph_pwr>;
237 vdd-s3-supply = <&vph_pwr>;
238 vdd-s4-supply = <&vph_pwr>;
239 vdd-s5-supply = <&vph_pwr>;
240 vdd-s6-supply = <&vph_pwr>;
241 vdd-s7-supply = <&vph_pwr>;
242 vdd-s8-supply = <&vph_pwr>;
243 vdd-s9-supply = <&vph_pwr>;
244 vdd-s10-supply = <&vph_pwr>;
245
246 vdd-l1-l12-supply = <&vreg_s1c_1p86>;
247 vdd-l2-l8-supply = <&vreg_s1c_1p86>;
248 vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
249 vdd-l6-l9-l11-supply = <&vreg_bob>;
250 vdd-l10-supply = <&vreg_s12b_1p25>;
251
252 vdd-bob-supply = <&vph_pwr>;
253
254 vreg_s1c_1p86: smps1 {
255 regulator-name = "vreg_s1c_1p86";
256 regulator-min-microvolt = <1856000>;
257 regulator-max-microvolt = <1880000>;
258 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
259 };
260
261 vreg_bob: bob {
262 regulator-name = "vreg_bob";
263 regulator-min-microvolt = <3008000>;
264 regulator-max-microvolt = <3960000>;
265 regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
266 };
267
268 vreg_l1c_1p8: ldo1 {
269 regulator-name = "vreg_l1c_1p8";
270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <1800000>;
272 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
273 };
274
275 vreg_l2c_1p8: ldo2 {
276 regulator-name = "vreg_l2c_1p8";
277 regulator-min-microvolt = <1800000>;
278 regulator-max-microvolt = <1800000>;
279 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
280 };
281
282 vreg_l6c_1p8: ldo6 {
283 regulator-name = "vreg_l6c_1p8";
284 regulator-min-microvolt = <1800000>;
285 regulator-max-microvolt = <2960000>;
286 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
287 };
288
289 vreg_l9c_2p96: ldo9 {
290 regulator-name = "vreg_l9c_2p96";
291 regulator-min-microvolt = <2960000>;
292 regulator-max-microvolt = <3008000>;
293 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
294 };
295
296 vreg_l10c_1p2: ldo10 {
297 regulator-name = "vreg_l10c_1p2";
298 regulator-min-microvolt = <1200000>;
299 regulator-max-microvolt = <1200000>;
300 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
301 };
302 };
303
304 regulators-2 {
305 compatible = "qcom,pmr735a-rpmh-regulators";
306 qcom,pmic-id = "e";
307
308 vdd-s1-supply = <&vph_pwr>;
309 vdd-s2-supply = <&vph_pwr>;
310 vdd-s3-supply = <&vph_pwr>;
311
312 vdd-l1-l2-supply = <&vreg_s2e_0p85>;
313 vdd-l3-supply = <&vreg_s1e_1p25>;
314 vdd-l4-supply = <&vreg_s1c_1p86>;
315 vdd-l5-l6-supply = <&vreg_s1c_1p86>;
316 vdd-l7-bob-supply = <&vreg_bob>;
317
318 vreg_s1e_1p25: smps1 {
319 regulator-name = "vreg_s1e_1p25";
320 regulator-min-microvolt = <1200000>;
321 regulator-max-microvolt = <1280000>;
322 };
323
324 vreg_s2e_0p85: smps2 {
325 regulator-name = "vreg_s2e_0p85";
326 regulator-min-microvolt = <950000>;
327 regulator-max-microvolt = <976000>;
328 };
329
330 vreg_s3e_2p20: smps3 {
331 regulator-name = "vreg_s3e_2p20";
332 regulator-min-microvolt = <2200000>;
333 regulator-max-microvolt = <2352000>;
334 };
335
336 vreg_l1e_0p9: ldo1 {
337 regulator-name = "vreg_l1e_0p9";
338 regulator-min-microvolt = <912000>;
339 regulator-max-microvolt = <912000>;
340 };
341
342 vreg_l2e_1p2: ldo2 {
343 regulator-name = "vreg_l2e_0p8";
344 regulator-min-microvolt = <1200000>;
345 regulator-max-microvolt = <1200000>;
346 };
347
348 vreg_l3e_1p2: ldo3 {
349 regulator-name = "vreg_l3e_1p2";
350 regulator-min-microvolt = <1200000>;
351 regulator-max-microvolt = <1200000>;
352 };
353
354 vreg_l4e_1p7: ldo4 {
355 regulator-name = "vreg_l4e_1p7";
356 regulator-min-microvolt = <1776000>;
357 regulator-max-microvolt = <1872000>;
358 };
359
360 vreg_l5e_0p8: ldo5 {
361 regulator-name = "vreg_l5e_0p8";
362 regulator-min-microvolt = <800000>;
363 regulator-max-microvolt = <800000>;
364 };
365
366 vreg_l6e_0p8: ldo6 {
367 regulator-name = "vreg_l6e_0p8";
368 regulator-min-microvolt = <480000>;
369 regulator-max-microvolt = <904000>;
370 };
371
372 vreg_l7e_2p8: ldo7 {
373 regulator-name = "vreg_l7e_2p8";
374 regulator-min-microvolt = <2800000>;
375 regulator-max-microvolt = <2800000>;
376 };
377 };
378};
379
380&cdsp {
381 status = "okay";
382 firmware-name = "qcom/sm8350/cdsp.mbn";
383};
384
385&dispcc {
386 status = "okay";
387};
388
389&mdss_dsi0 {
390 vdda-supply = <&vreg_l6b_1p2>;
391 status = "okay";
392
393 ports {
394 port@1 {
395 endpoint {
396 remote-endpoint = <&lt9611_a>;
397 data-lanes = <0 1 2 3>;
398 };
399 };
400 };
401};
402
403&mdss_dsi0_phy {
404 vdds-supply = <&vreg_l5b_0p88>;
405 status = "okay";
406};
407
408&gpi_dma1 {
409 status = "okay";
410};
411
412&gpu {
413 status = "okay";
414
415 zap-shader {
416 firmware-name = "qcom/sm8350/a660_zap.mbn";
417 };
418};
419
420&i2c13 {
421 clock-frequency = <100000>;
422
423 status = "okay";
424
425 typec-mux@42 {
426 compatible = "fcs,fsa4480";
427 reg = <0x42>;
428
429 interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>;
430
431 vcc-supply = <&vreg_bob>;
432 mode-switch;
433 orientation-switch;
434
435 port {
436 fsa4480_sbu_mux: endpoint {
437 remote-endpoint = <&pmic_glink_sbu>;
438 };
439 };
440 };
441};
442
443&i2c15 {
444 clock-frequency = <400000>;
445 status = "okay";
446
447 lt9611_codec: hdmi-bridge@2b {
448 compatible = "lontium,lt9611uxc";
449 reg = <0x2b>;
450
451 interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
452 reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
453
454 vdd-supply = <&lt9611_1v2>;
455 vcc-supply = <&lt9611_3v3>;
456
457 pinctrl-names = "default";
458 pinctrl-0 = <&lt9611_state>;
459
460 ports {
461 #address-cells = <1>;
462 #size-cells = <0>;
463
464 port@0 {
465 reg = <0>;
466
467 lt9611_a: endpoint {
468 remote-endpoint = <&mdss_dsi0_out>;
469 };
470 };
471
472 port@2 {
473 reg = <2>;
474
475 lt9611_out: endpoint {
476 remote-endpoint = <&hdmi_con>;
477 };
478 };
479 };
480 };
481};
482
483&mdss {
484 status = "okay";
485};
486
487&mdss_dp {
488 status = "okay";
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame^]489};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]490
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame^]491&mdss_dp_out {
492 data-lanes = <0 1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]493};
494
495&mpss {
496 status = "okay";
497 firmware-name = "qcom/sm8350/modem.mbn";
498};
499
500&pcie0 {
501 pinctrl-names = "default";
502 pinctrl-0 = <&pcie0_default_state>;
503
504 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
505 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
506
507 status = "okay";
508};
509
510&pcie0_phy {
511 vdda-phy-supply = <&vreg_l5b_0p88>;
512 vdda-pll-supply = <&vreg_l6b_1p2>;
513
514 status = "okay";
515};
516
517&pcie1 {
518 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
519 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
520
521 pinctrl-names = "default";
522 pinctrl-0 = <&pcie1_default_state>;
523
524 status = "okay";
525};
526
527&pcie1_phy {
528 status = "okay";
529 vdda-phy-supply = <&vreg_l5b_0p88>;
530 vdda-pll-supply = <&vreg_l6b_1p2>;
531};
532
533&qupv3_id_0 {
534 status = "okay";
535};
536
537&qupv3_id_1 {
538 status = "okay";
539};
540
541&qupv3_id_2 {
542 status = "okay";
543};
544
545&sdhc_2 {
546 cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
547 pinctrl-names = "default", "sleep";
548 pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
549 pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
550 vmmc-supply = <&vreg_l9c_2p96>;
551 vqmmc-supply = <&vreg_l6c_1p8>;
552 no-sdio;
553 no-mmc;
554 status = "okay";
555};
556
557&slpi {
558 status = "okay";
559 firmware-name = "qcom/sm8350/slpi.mbn";
560};
561
562&tlmm {
563 gpio-reserved-ranges = <52 8>;
564
565 gpio-line-names =
566 "APPS_I2C_SDA", /* GPIO_0 */
567 "APPS_I2C_SCL",
568 "FSA_INT_N",
569 "USER_LED3_EN",
570 "SMBUS_SDA_1P8",
571 "SMBUS_SCL_1P8",
572 "2M2_3P3_EN",
573 "ALERT_DUAL_M2_N",
574 "EXP_UART_CTS",
575 "EXP_UART_RFR",
576 "EXP_UART_TX", /* GPIO_10 */
577 "EXP_UART_RX",
578 "NC",
579 "NC",
580 "RCM_MARKER1",
581 "WSA0_EN",
582 "CAM1_RESET_N",
583 "CAM0_RESET_N",
584 "DEBUG_UART_TX",
585 "DEBUG_UART_RX",
586 "TS_I2C_SDA", /* GPIO_20 */
587 "TS_I2C_SCL",
588 "TS_RESET_N",
589 "TS_INT_N",
590 "DISP0_RESET_N",
591 "DISP1_RESET_N",
592 "ETH_RESET",
593 "RCM_MARKER2",
594 "CAM_DC_MIPI_MUX_EN",
595 "CAM_DC_MIPI_MUX_SEL",
596 "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
597 "AFC_PHY_TA_D_MINUS",
598 "PM8008_1_IRQ",
599 "PM8008_1_RESET_N",
600 "PM8008_2_IRQ",
601 "PM8008_2_RESET_N",
602 "CAM_DC_I3C_SDA",
603 "CAM_DC_I3C_SCL",
604 "FP_INT_N",
605 "FP_WUHB_INT_N",
606 "SMB_SPMI_DATA", /* GPIO_40 */
607 "SMB_SPMI_CLK",
608 "USB_HUB_RESET",
609 "FORCE_USB_BOOT",
610 "LRF_IRQ",
611 "NC",
612 "IMU2_INT",
613 "HDMI_3P3_EN",
614 "HDMI_RSTN",
615 "HDMI_1P2_EN",
616 "HDMI_INT", /* GPIO_50 */
617 "USB1_ID",
618 "FP_SPI_MISO",
619 "FP_SPI_MOSI",
620 "FP_SPI_CLK",
621 "FP_SPI_CS_N",
622 "NFC_ESE_SPI_MISO",
623 "NFC_ESE_SPI_MOSI",
624 "NFC_ESE_SPI_CLK",
625 "NFC_ESE_SPI_CS",
626 "NFC_I2C_SDA", /* GPIO_60 */
627 "NFC_I2C_SCLC",
628 "NFC_EN",
629 "NFC_CLK_REQ",
630 "HST_WLAN_EN",
631 "HST_BT_EN",
632 "HST_SW_CTRL",
633 "NC",
634 "HST_BT_UART_CTS",
635 "HST_BT_UART_RFR",
636 "HST_BT_UART_TX", /* GPIO_70 */
637 "HST_BT_UART_RX",
638 "CAM_DC_SPI0_MISO",
639 "CAM_DC_SPI0_MOSI",
640 "CAM_DC_SPI0_CLK",
641 "CAM_DC_SPI0_CS_N",
642 "CAM_DC_SPI1_MISO",
643 "CAM_DC_SPI1_MOSI",
644 "CAM_DC_SPI1_CLK",
645 "CAM_DC_SPI1_CS_N",
646 "HALL_INT_N", /* GPIO_80 */
647 "USB_PHY_PS",
648 "MDP_VSYNC_P",
649 "MDP_VSYNC_S",
650 "ETH_3P3_EN",
651 "RADAR_INT",
652 "NFC_DWL_REQ",
653 "SM_GPIO_87",
654 "WCD_RESET_N",
655 "ALSP_INT_N",
656 "PRESS_INT", /* GPIO_90 */
657 "SAR_INT_N",
658 "SD_CARD_DET_N",
659 "NC",
660 "PCIE0_RESET_N",
661 "PCIE0_CLK_REQ_N",
662 "PCIE0_WAKE_N",
663 "PCIE1_RESET_N",
664 "PCIE1_CLK_REQ_N",
665 "PCIE1_WAKE_N",
666 "CAM_MCLK0", /* GPIO_100 */
667 "CAM_MCLK1",
668 "CAM_MCLK2",
669 "CAM_MCLK3",
670 "CAM_MCLK4",
671 "CAM_MCLK5",
672 "CAM2_RESET_N",
673 "CCI_I2C0_SDA",
674 "CCI_I2C0_SCL",
675 "CCI_I2C1_SDA",
676 "CCI_I2C1_SCL", /* GPIO_110 */
677 "CCI_I2C2_SDA",
678 "CCI_I2C2_SCL",
679 "CCI_I2C3_SDA",
680 "CCI_I2C3_SCL",
681 "CAM5_RESET_N",
682 "CAM4_RESET_N",
683 "CAM3_RESET_N",
684 "IMU1_INT",
685 "MAG_INT_N",
686 "MI2S2_I2S_SCK", /* GPIO_120 */
687 "MI2S2_I2S_DAT0",
688 "MI2S2_I2S_WS",
689 "HIFI_DAC_I2S_MCLK",
690 "MI2S2_I2S_DAT1",
691 "HIFI_DAC_I2S_SCK",
692 "HIFI_DAC_I2S_DAT0",
693 "NC",
694 "HIFI_DAC_I2S_WS",
695 "HST_BT_WLAN_SLIMBUS_CLK",
696 "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */
697 "BT_LED_EN",
698 "WLAN_LED_EN",
699 "NC",
700 "NC",
701 "NC",
702 "UIM2_PRESENT",
703 "NC",
704 "NC",
705 "NC",
706 "UIM1_PRESENT", /* GPIO_140 */
707 "NC",
708 "SM_RFFE0_DATA",
709 "NC",
710 "SM_RFFE1_DATA",
711 "SM_MSS_GRFC4",
712 "SM_MSS_GRFC5",
713 "SM_MSS_GRFC6",
714 "SM_MSS_GRFC7",
715 "SM_RFFE4_CLK",
716 "SM_RFFE4_DATA", /* GPIO_150 */
717 "WLAN_COEX_UART1_RX",
718 "WLAN_COEX_UART1_TX",
719 "HST_SW_CTRL",
720 "DSI0_STATUS",
721 "DSI1_STATUS",
722 "APPS_PBL_BOOT_SPEED_1",
723 "APPS_BOOT_FROM_ROM",
724 "APPS_PBL_BOOT_SPEED_0",
725 "QLINK0_REQ",
726 "QLINK0_EN", /* GPIO_160 */
727 "QLINK0_WMSS_RESET_N",
728 "NC",
729 "NC",
730 "NC",
731 "NC",
732 "NC",
733 "NC",
734 "WCD_SWR_TX_CLK",
735 "WCD_SWR_TX_DATA0",
736 "WCD_SWR_TX_DATA1", /* GPIO_170 */
737 "WCD_SWR_RX_CLK",
738 "WCD_SWR_RX_DATA0",
739 "WCD_SWR_RX_DATA1",
740 "DMIC01_CLK",
741 "DMIC01_DATA",
742 "DMIC23_CLK",
743 "DMIC23_DATA",
744 "WSA_SWR_CLK",
745 "WSA_SWR_DATA",
746 "DMIC45_CLK", /* GPIO_180 */
747 "DMIC45_DATA",
748 "WCD_SWR_TX_DATA2",
749 "SENSOR_I3C_SDA",
750 "SENSOR_I3C_SCL",
751 "CAM_OIS0_I3C_SDA",
752 "CAM_OIS0_I3C_SCL",
753 "IMU_SPI_MISO",
754 "IMU_SPI_MOSI",
755 "IMU_SPI_CLK",
756 "IMU_SPI_CS_N", /* GPIO_190 */
757 "MAG_I2C_SDA",
758 "MAG_I2C_SCL",
759 "SENSOR_I2C_SDA",
760 "SENSOR_I2C_SCL",
761 "RADAR_SPI_MISO",
762 "RADAR_SPI_MOSI",
763 "RADAR_SPI_CLK",
764 "RADAR_SPI_CS_N",
765 "HST_BLE_UART_TX",
766 "HST_BLE_UART_RX", /* GPIO_200 */
767 "HST_WLAN_UART_TX",
768 "HST_WLAN_UART_RX";
769
770 pcie0_default_state: pcie0-default-state {
771 perst-pins {
772 pins = "gpio94";
773 function = "gpio";
774 drive-strength = <2>;
775 bias-pull-down;
776 };
777
778 clkreq-pins {
779 pins = "gpio95";
780 function = "pcie0_clkreqn";
781 drive-strength = <2>;
782 bias-pull-up;
783 };
784
785 wake-pins {
786 pins = "gpio96";
787 function = "gpio";
788 drive-strength = <2>;
789 bias-pull-up;
790 };
791 };
792
793 pcie1_default_state: pcie1-default-state {
794 perst-pins {
795 pins = "gpio97";
796 function = "gpio";
797 drive-strength = <2>;
798 bias-pull-down;
799 };
800
801 clkreq-pins {
802 pins = "gpio98";
803 function = "pcie1_clkreqn";
804 drive-strength = <2>;
805 bias-pull-up;
806 };
807
808 wake-pins {
809 pins = "gpio99";
810 function = "gpio";
811 drive-strength = <2>;
812 bias-pull-up;
813 };
814 };
815
816 sdc2_card_det_n: sd-card-det-n-state {
817 pins = "gpio92";
818 function = "gpio";
819 drive-strength = <2>;
820 bias-pull-up;
821 };
822};
823
824&uart2 {
825 status = "okay";
826};
827
828&ufs_mem_hc {
829 status = "okay";
830
831 reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>;
832
833 vcc-supply = <&vreg_l7b_2p96>;
834 vcc-max-microamp = <800000>;
835 vccq-supply = <&vreg_l9b_1p2>;
836 vccq-max-microamp = <900000>;
837 vdd-hba-supply = <&vreg_l9b_1p2>;
838};
839
840&ufs_mem_phy {
841 status = "okay";
842
843 vdda-phy-supply = <&vreg_l5b_0p88>;
844 vdda-pll-supply = <&vreg_l6b_1p2>;
845};
846
847&usb_1 {
848 status = "okay";
849};
850
851&usb_1_dwc3 {
852 dr_mode = "otg";
853 usb-role-switch;
854};
855
856&usb_1_dwc3_hs {
857 remote-endpoint = <&pmic_glink_hs_in>;
858};
859
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]860&usb_1_hsphy {
861 status = "okay";
862
863 vdda-pll-supply = <&vreg_l5b_0p88>;
864 vdda18-supply = <&vreg_l1c_1p8>;
865 vdda33-supply = <&vreg_l2b_3p07>;
866};
867
868&usb_1_qmpphy {
869 status = "okay";
870
871 vdda-phy-supply = <&vreg_l6b_1p2>;
872 vdda-pll-supply = <&vreg_l1b_0p88>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]873};
874
875&usb_1_qmpphy_out {
876 remote-endpoint = <&pmic_glink_ss_in>;
877};
878
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]879&usb_2 {
880 status = "okay";
881};
882
883&usb_2_dwc3 {
884 dr_mode = "host";
885
886 pinctrl-names = "default";
887 pinctrl-0 = <&usb_hub_enabled_state>;
888};
889
890&usb_2_hsphy {
891 status = "okay";
892
893 vdda-pll-supply = <&vreg_l5b_0p88>;
894 vdda18-supply = <&vreg_l1c_1p8>;
895 vdda33-supply = <&vreg_l2b_3p07>;
896};
897
898&usb_2_qmpphy {
899 status = "okay";
900
901 vdda-phy-supply = <&vreg_l6b_1p2>;
902 vdda-pll-supply = <&vreg_l5b_0p88>;
903};
904
905/* PINCTRL - additions to nodes defined in sm8350.dtsi */
906
907&tlmm {
908 usb_hub_enabled_state: usb-hub-enabled-state {
909 pins = "gpio42";
910 function = "gpio";
911
912 drive-strength = <2>;
913 output-low;
914 };
915
916 lt9611_state: lt9611-state {
917 rst-pins {
918 pins = "gpio48";
919 function = "gpio";
920
921 output-high;
922 input-disable;
923 };
924
925 irq-pins {
926 pins = "gpio50";
927 function = "gpio";
928 bias-disable;
929 };
930 };
931};