| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2017 Marvell Technology Group Ltd. |
| 4 | * |
| 5 | * Device Tree file for the Armada 70x0 SoC |
| 6 | */ |
| 7 | |
| 8 | / { |
| 9 | aliases { |
| 10 | gpio1 = &cp0_gpio1; |
| 11 | gpio2 = &cp0_gpio2; |
| 12 | spi1 = &cp0_spi0; |
| 13 | spi2 = &cp0_spi1; |
| 14 | }; |
| 15 | }; |
| 16 | |
| 17 | /* |
| 18 | * Instantiate the CP110 |
| 19 | */ |
| 20 | #define CP11X_NAME cp0 |
| 21 | #define CP11X_BASE f2000000 |
| 22 | #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) |
| 23 | #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 |
| 24 | #define CP11X_PCIE0_BASE f2600000 |
| 25 | #define CP11X_PCIE1_BASE f2620000 |
| 26 | #define CP11X_PCIE2_BASE f2640000 |
| 27 | |
| 28 | #include "armada-cp110.dtsi" |
| 29 | |
| 30 | #undef CP11X_NAME |
| 31 | #undef CP11X_BASE |
| 32 | #undef CP11X_PCIEx_MEM_BASE |
| 33 | #undef CP11X_PCIEx_MEM_SIZE |
| 34 | #undef CP11X_PCIE0_BASE |
| 35 | #undef CP11X_PCIE1_BASE |
| 36 | #undef CP11X_PCIE2_BASE |
| 37 | |
| 38 | &cp0_gpio1 { |
| 39 | status = "okay"; |
| 40 | }; |
| 41 | |
| 42 | &cp0_gpio2 { |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | |
| 46 | &cp0_syscon0 { |
| 47 | cp0_pinctrl: pinctrl { |
| 48 | compatible = "marvell,armada-7k-pinctrl"; |
| 49 | |
| 50 | nand_pins: nand-pins { |
| 51 | marvell,pins = |
| 52 | "mpp15", "mpp16", "mpp17", "mpp18", |
| 53 | "mpp19", "mpp20", "mpp21", "mpp22", |
| 54 | "mpp23", "mpp24", "mpp25", "mpp26", |
| 55 | "mpp27"; |
| 56 | marvell,function = "dev"; |
| 57 | }; |
| 58 | |
| 59 | nand_rb: nand-rb { |
| 60 | marvell,pins = "mpp13"; |
| 61 | marvell,function = "nf"; |
| 62 | }; |
| 63 | }; |
| 64 | }; |