| Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ |
| 2 | /* |
| 3 | * Copyright 2024 NXP |
| 4 | */ |
| 5 | |
| 6 | #ifndef __IMX95_POWER_H__ |
| 7 | #define __IMX95_POWER_H__ |
| 8 | |
| 9 | #define IMX95_PD_ANA 0 |
| 10 | #define IMX95_PD_AON 1 |
| 11 | #define IMX95_PD_BBSM 2 |
| 12 | #define IMX95_PD_CAMERA 3 |
| 13 | #define IMX95_PD_CCMSRCGPC 4 |
| 14 | #define IMX95_PD_A55C0 5 |
| 15 | #define IMX95_PD_A55C1 6 |
| 16 | #define IMX95_PD_A55C2 7 |
| 17 | #define IMX95_PD_A55C3 8 |
| 18 | #define IMX95_PD_A55C4 9 |
| 19 | #define IMX95_PD_A55C5 10 |
| 20 | #define IMX95_PD_A55P 11 |
| 21 | #define IMX95_PD_DDR 12 |
| 22 | #define IMX95_PD_DISPLAY 13 |
| 23 | #define IMX95_PD_GPU 14 |
| 24 | #define IMX95_PD_HSIO_TOP 15 |
| 25 | #define IMX95_PD_HSIO_WAON 16 |
| 26 | #define IMX95_PD_M7 17 |
| 27 | #define IMX95_PD_NETC 18 |
| 28 | #define IMX95_PD_NOC 19 |
| 29 | #define IMX95_PD_NPU 20 |
| 30 | #define IMX95_PD_VPU 21 |
| 31 | #define IMX95_PD_WAKEUP 22 |
| 32 | |
| 33 | #define IMX95_PERF_ELE 0 |
| 34 | #define IMX95_PERF_M33 1 |
| 35 | #define IMX95_PERF_WAKEUP 2 |
| 36 | #define IMX95_PERF_M7 3 |
| 37 | #define IMX95_PERF_DRAM 4 |
| 38 | #define IMX95_PERF_HSIO 5 |
| 39 | #define IMX95_PERF_NPU 6 |
| 40 | #define IMX95_PERF_NOC 7 |
| 41 | #define IMX95_PERF_A55 8 |
| 42 | #define IMX95_PERF_GPU 9 |
| 43 | #define IMX95_PERF_VPU 10 |
| 44 | #define IMX95_PERF_CAM 11 |
| 45 | #define IMX95_PERF_DISP 12 |
| 46 | |
| 47 | #endif |