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git01.mediatek.com / filogic / uboot / 6b642aca7f571e777924f50732f530fd94b03bfb / . / src / arm64 / freescale / imx95-19x19-evk.dts
blob: d14a54ab4fd47362510e2ba644606bcc4174615f [file] [log] [blame]
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2024 NXP
4 */
5
6/dts-v1/;
7
8#include "imx95.dtsi"
9
10/ {
11 model = "NXP i.MX95 19X19 board";
12 compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
13
14 aliases {
15 mmc0 = &usdhc1;
16 mmc1 = &usdhc2;
17 serial0 = &lpuart1;
18 };
19
20 chosen {
21 stdout-path = &lpuart1;
22 };
23
24 memory@80000000 {
25 device_type = "memory";
26 reg = <0x0 0x80000000 0 0x80000000>;
27 };
28
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
32 ranges;
33
34 linux_cma: linux,cma {
35 compatible = "shared-dma-pool";
36 alloc-ranges = <0 0x80000000 0 0x7f000000>;
37 size = <0 0x3c000000>;
38 linux,cma-default;
39 reusable;
40 };
41 };
42
43 reg_m2_pwr: regulator-m2-pwr {
44 compatible = "regulator-fixed";
45 regulator-name = "M.2-power";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>;
49 enable-active-high;
50 };
51
52 reg_pcie0: regulator-pcie {
53 compatible = "regulator-fixed";
54 regulator-name = "PCIE_WLAN_EN";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 vin-supply = <&reg_m2_pwr>;
58 gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>;
59 enable-active-high;
60 };
61
62 reg_slot_pwr: regulator-slot-pwr {
63 compatible = "regulator-fixed";
64 regulator-name = "PCIe slot-power";
65 regulator-min-microvolt = <3300000>;
66 regulator-max-microvolt = <3300000>;
67 gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>;
68 enable-active-high;
69 };
70
71 reg_usdhc2_vmmc: regulator-usdhc2 {
72 compatible = "regulator-fixed";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
75 regulator-name = "VDD_SD2_3V3";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
79 enable-active-high;
80 off-on-delay-us = <12000>;
81 };
82};
83
84&lpi2c7 {
85 clock-frequency = <1000000>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_lpi2c7>;
88 status = "okay";
89
90 i2c7_pcal6524: i2c7-gpio@22 {
91 compatible = "nxp,pcal6524";
92 reg = <0x22>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_i2c7_pcal6524>;
95 gpio-controller;
96 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <2>;
99 interrupt-parent = <&gpio5>;
100 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
101 };
102};
103
104&lpuart1 {
105 /* console */
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_uart1>;
108 status = "okay";
109};
110
111&mu7 {
112 status = "okay";
113};
114
115&pcie0 {
116 pinctrl-0 = <&pinctrl_pcie0>;
117 pinctrl-names = "default";
118 reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
119 vpcie-supply = <&reg_pcie0>;
120 status = "okay";
121};
122
123&pcie1 {
124 pinctrl-0 = <&pinctrl_pcie1>;
125 pinctrl-names = "default";
126 reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
127 vpcie-supply = <&reg_slot_pwr>;
128 status = "okay";
129};
130
131&usdhc1 {
132 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
133 pinctrl-0 = <&pinctrl_usdhc1>;
134 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
135 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
136 pinctrl-3 = <&pinctrl_usdhc1>;
137 bus-width = <8>;
138 non-removable;
139 no-sdio;
140 no-sd;
141 status = "okay";
142};
143
144&usdhc2 {
145 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
146 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
147 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
148 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
149 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
150 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
151 vmmc-supply = <&reg_usdhc2_vmmc>;
152 bus-width = <4>;
153 status = "okay";
154};
155
156&wdog3 {
157 fsl,ext-reset-output;
158 status = "okay";
159};
160
161&scmi_iomuxc {
162 pinctrl_i2c7_pcal6524: i2c7pcal6524grp {
163 fsl,pins = <
164 IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
165 >;
166 };
167
168 pinctrl_lpi2c7: lpi2c7grp {
169 fsl,pins = <
170 IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e
171 IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e
172 >;
173 };
174
175 pinctrl_pcie0: pcie0grp {
176 fsl,pins = <
177 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e
178 >;
179 };
180
181 pinctrl_pcie1: pcie1grp {
182 fsl,pins = <
183 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e
184 >;
185 };
186
187 pinctrl_uart1: uart1grp {
188 fsl,pins = <
189 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
190 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
191 >;
192 };
193
194 pinctrl_usdhc1: usdhc1grp {
195 fsl,pins = <
196 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
197 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
198 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
199 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
200 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
201 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
202 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
203 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
204 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
205 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
206 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
207 >;
208 };
209
210 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
211 fsl,pins = <
212 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
213 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
214 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
215 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
216 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
217 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
218 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
219 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
220 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
221 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
222 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
223 >;
224 };
225
226 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
227 fsl,pins = <
228 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
229 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
230 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
231 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
232 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
233 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
234 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
235 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
236 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
237 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
238 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
239 >;
240 };
241
242 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
243 fsl,pins = <
244 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
245 >;
246 };
247
248 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
249 fsl,pins = <
250 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
251 >;
252 };
253
254 pinctrl_usdhc2: usdhc2grp {
255 fsl,pins = <
256 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
257 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
258 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
259 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
260 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
261 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
262 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
263 >;
264 };
265
266 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
267 fsl,pins = <
268 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
269 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
270 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
271 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
272 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
273 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
274 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
275 >;
276 };
277
278 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
279 fsl,pins = <
280 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
281 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
282 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
283 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
284 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
285 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
286 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
287 >;
288 };
289};