src/arm64/freescale/imx8qm-mek.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

/dts-v1/;

#include "imx8qm.dtsi"

/ {
	model = "Freescale i.MX8QM MEK";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	chosen {
		stdout-path = &lpuart0;
	};

	cpus {
		/delete-node/ cpu-map;
		/delete-node/ cpu@100;
		/delete-node/ cpu@101;
	};

	thermal-zones {
		/delete-node/ cpu1-thermal;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	reg_usdhc2_vmmc: usdhc2-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_fec2_supply: regulator-fec2-nvcc {
		compatible = "regulator-fixed";
		regulator-name = "fec2_nvcc";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can01_en: regulator-can01-gen {
		compatible = "regulator-fixed";
		regulator-name = "can01-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can2_en: regulator-can2-gen {
		compatible = "regulator-fixed";
		regulator-name = "can2-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can01_stby: regulator-can01-stby {
		compatible = "regulator-fixed";
		regulator-name = "can01-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can01_en>;
	};

	reg_can2_stby: regulator-can2-stby {
		compatible = "regulator-fixed";
		regulator-name = "can2-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can2_en>;
	};

	reg_vref_1v8: regulator-adc-vref {
		compatible = "regulator-fixed";
		regulator-name = "vref_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	bt_sco_codec: audio-codec-bt {
		compatible = "linux,bt-sco";
		#sound-dai-cells = <1>;
	};

	sound-bt-sco {
		compatible = "simple-audio-card";
		simple-audio-card,name = "bt-sco-audio";
		simple-audio-card,format = "dsp_a";
		simple-audio-card,bitclock-inversion;
		simple-audio-card,frame-master = <&btcpu>;
		simple-audio-card,bitclock-master = <&btcpu>;

		btcpu: simple-audio-card,cpu {
			sound-dai = <&sai0>;
			dai-tdm-slot-num = <2>;
			dai-tdm-slot-width = <16>;
		};

		simple-audio-card,codec {
			sound-dai = <&bt_sco_codec 1>;
		};
	};

	sound-wm8960 {
		compatible = "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		audio-cpu = <&sai1>;
		audio-codec = <&wm8960>;
		hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
		audio-routing =	"Headphone Jack", "HP_L",
				"Headphone Jack", "HP_R",
				"Ext Spk", "SPK_LP",
				"Ext Spk", "SPK_LN",
				"Ext Spk", "SPK_RP",
				"Ext Spk", "SPK_RN",
				"LINPUT1", "Mic Jack",
				"Mic Jack", "MICB";
	};
};

&adc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc0>;
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&amix {
	status = "okay";
};

&asrc0 {
	fsl,asrc-rate = <48000>;
	status = "okay";
};

&cm41_i2c {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_cm41_i2c>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&cm41_intmux {
	status = "okay";
};

&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	accelerometer@19 {
		compatible = "st,lsm303agr-accel";
		reg = <0x19>;
	};

	gyrometer@20 {
		compatible = "nxp,fxas21002c";
		reg = <0x20>;
	};

	light-sensor@44 {
		compatible = "isil,isl29023";
		reg = <0x44>;
		interrupt-parent = <&lsio_gpio4>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
	};

	pressure-sensor@60 {
		compatible = "fsl,mpl3115";
		reg = <0x60>;
	};

	max7322: gpio@68 {
		compatible = "maxim,max7322";
		reg = <0x68>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	gyrometer@69 {
		compatible = "st,l3g4200d-gyro";
		reg = <0x69>;
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
	status = "okay";

	wm8960: audio-codec@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
		clock-names = "mclk";
		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
				  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
				  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
				  <&mclkout0_lpcg IMX_LPCG_CLK_0>;
		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
		wlf,shared-lrclk;
		wlf,hp-cfg = <2 2 3>;
		wlf,gpio-cfg = <1 3>;
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can01_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can01_stby>;
	status = "okay";
};

&flexcan3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan3>;
	xceiver-supply = <&reg_can2_stby>;
	status = "okay";
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "okay";
};

&lpuart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "okay";
};

&lpspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
	cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev0: spi@0 {
		reg = <0>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <30000000>;
	};
};

&lsio_mu5 {
	status = "okay";
};

&lsio_mu6 {
	status = "okay";
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <133000000>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_fec2_supply>;
	nvmem-cells = <&fec_mac1>;
	nvmem-cell-names = "mac-address";
	rx-internal-delay-ps = <2000>;
	fsl,magic-packet;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&sai0 {
	#sound-dai-cells = <0>;
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			  <&sai0_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai0>;
	status = "okay";
};

&sai1 {
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			  <&sai1_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};

&sai6 {
	assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
			  <&sai6_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
	fsl,sai-asynchronous;
	status = "okay";
};

&sai7 {
	assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
			  <&sai7_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
	fsl,sai-asynchronous;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0			0x0600004c
			IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31			0x0600004c
		>;
	};

	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL			0x06000021
			IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA			0x06000021
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
			IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpio-grp {
		fsl,pins = <
			IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14		0xc600004c
			IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15	0xc600004c
		>;
	};

	pinctrl_adc0: adc0grp {
		fsl,pins = <
			IMX8QM_ADC_IN0_DMA_ADC0_IN0				0xc0000060
		>;
	};

	pinctrl_cm41_i2c: cm41i2cgrp {
		fsl,pins = <
			IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA			0x0600004c
			IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL			0x0600004c
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
		>;
	};

	pinctrl_lpspi2: lpspi2grp {
		fsl,pins = <
			IMX8QM_SPI2_SCK_DMA_SPI2_SCK		0x06000040
			IMX8QM_SPI2_SDO_DMA_SPI2_SDO		0x06000040
			IMX8QM_SPI2_SDI_DMA_SPI2_SDI		0x06000040
		>;
	};

	pinctrl_lpspi2_cs: lpspi2csgrp {
		fsl,pins = <
			IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10		0x21
		>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
			IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
			IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
			IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
			IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
			IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
			IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B     0x06000021
			IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
			IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
			IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
			IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
			IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
			IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
			IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
			IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
			IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x06000021
		>;
	};

	pinctrl_fec2: fec2grp {
		fsl,pins = <
			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0
			IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
			IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC		0x00000060
			IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0		0x00000060
			IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1		0x00000060
			IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2		0x00000060
			IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3		0x00000060
			IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC		0x00000060
			IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
			IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0		0x00000060
			IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1		0x00000060
			IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2		0x00000060
			IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3		0x00000060
		>;
	};

	pinctrl_flexcan1: flexcan0grp {
		fsl,pins = <
			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x21
			IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX			0x21
		>;
	};

	pinctrl_flexcan2: flexcan1grp {
		fsl,pins = <
			IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX			0x21
			IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX			0x21
		>;
	};

	pinctrl_flexcan3: flexcan3grp {
		fsl,pins = <
			IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX			0x21
			IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX			0x21
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
		>;
	};

	pinctrl_lpuart2: lpuart2grp {
		fsl,pins = <
			IMX8QM_UART0_RTS_B_DMA_UART2_RX				0x06000020
			IMX8QM_UART0_CTS_B_DMA_UART2_TX				0x06000020
		>;
	};

	pinctrl_lpuart3: lpuart3grp {
		fsl,pins = <
			IMX8QM_M41_GPIO0_00_DMA_UART3_RX			0x06000020
			IMX8QM_M41_GPIO0_01_DMA_UART3_TX			0x06000020
		>;
	};

	pinctrl_sai0: sai0grp {
		fsl,pins = <
			IMX8QM_SPI0_CS1_AUD_SAI0_TXC				0x0600004c
			IMX8QM_SPI2_CS1_AUD_SAI0_TXFS				0x0600004c
			IMX8QM_SAI1_RXFS_AUD_SAI0_RXD				0x0600004c
			IMX8QM_SAI1_RXC_AUD_SAI0_TXD				0x0600006c
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			IMX8QM_SAI1_RXD_AUD_SAI1_RXD				0x06000040
			IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS				0x06000040
			IMX8QM_SAI1_TXD_AUD_SAI1_TXD				0x06000060
			IMX8QM_SAI1_TXC_AUD_SAI1_TXC				0x06000040
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
		>;
	};
};