Bindings/clock/mediatek,mt6795-clock.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Functional Clock Controller for MT6795

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description: |
  The clock architecture in MediaTek like below
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The devices provide clock gate control in different IP blocks.

properties:
  compatible:
    enum:
      - mediatek,mt6795-mfgcfg
      - mediatek,mt6795-vdecsys
      - mediatek,mt6795-vencsys

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        mfgcfg: clock-controller@13000000 {
            compatible = "mediatek,mt6795-mfgcfg";
            reg = <0 0x13000000 0 0x1000>;
            #clock-cells = <1>;
        };

        vdecsys: clock-controller@16000000 {
            compatible = "mediatek,mt6795-vdecsys";
            reg = <0 0x16000000 0 0x1000>;
            #clock-cells = <1>;
        };

        vencsys: clock-controller@18000000 {
            compatible = "mediatek,mt6795-vencsys";
            reg = <0 0x18000000 0 0x1000>;
            #clock-cells = <1>;
        };
    };