Michal Simek | 4b066a1 | 2018-08-22 14:55:27 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2016 - 2018 Xilinx, Inc. |
| 4 | * Michal Simek <michal.simek@xilinx.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/armv8/mmu.h> |
| 9 | #include <asm/io.h> |
Siva Durga Prasad Paladugu | 775aa95 | 2019-01-08 21:47:26 +0530 | [diff] [blame] | 10 | #include <asm/arch/hardware.h> |
| 11 | #include <asm/arch/sys_proto.h> |
| 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
Michal Simek | 4b066a1 | 2018-08-22 14:55:27 +0200 | [diff] [blame] | 14 | |
| 15 | static struct mm_region versal_mem_map[] = { |
| 16 | { |
| 17 | .virt = 0x0UL, |
| 18 | .phys = 0x0UL, |
| 19 | .size = 0x80000000UL, |
| 20 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 21 | PTE_BLOCK_INNER_SHARE |
| 22 | }, { |
| 23 | .virt = 0x80000000UL, |
| 24 | .phys = 0x80000000UL, |
| 25 | .size = 0x70000000UL, |
| 26 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 27 | PTE_BLOCK_NON_SHARE | |
| 28 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 29 | }, { |
| 30 | .virt = 0xf0000000UL, |
| 31 | .phys = 0xf0000000UL, |
| 32 | .size = 0x0fe00000UL, |
| 33 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 34 | PTE_BLOCK_NON_SHARE | |
| 35 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 36 | }, { |
| 37 | .virt = 0xffe00000UL, |
| 38 | .phys = 0xffe00000UL, |
| 39 | .size = 0x00200000UL, |
| 40 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 41 | PTE_BLOCK_INNER_SHARE |
| 42 | }, { |
| 43 | .virt = 0x400000000UL, |
| 44 | .phys = 0x400000000UL, |
| 45 | .size = 0x200000000UL, |
| 46 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 47 | PTE_BLOCK_NON_SHARE | |
| 48 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 49 | }, { |
| 50 | .virt = 0x600000000UL, |
| 51 | .phys = 0x600000000UL, |
| 52 | .size = 0x800000000UL, |
| 53 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 54 | PTE_BLOCK_INNER_SHARE |
| 55 | }, { |
| 56 | .virt = 0xe00000000UL, |
| 57 | .phys = 0xe00000000UL, |
| 58 | .size = 0xf200000000UL, |
| 59 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 60 | PTE_BLOCK_NON_SHARE | |
| 61 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 62 | }, { |
| 63 | /* List terminator */ |
| 64 | 0, |
| 65 | } |
| 66 | }; |
| 67 | |
| 68 | struct mm_region *mem_map = versal_mem_map; |
| 69 | |
| 70 | u64 get_page_table_size(void) |
| 71 | { |
| 72 | return 0x14000; |
| 73 | } |
Siva Durga Prasad Paladugu | 775aa95 | 2019-01-08 21:47:26 +0530 | [diff] [blame] | 74 | |
| 75 | #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) |
| 76 | int reserve_mmu(void) |
| 77 | { |
| 78 | tcm_init(TCM_LOCK); |
| 79 | gd->arch.tlb_size = PGTABLE_SIZE; |
| 80 | gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR; |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | #endif |
Michal Simek | c3c3106 | 2018-09-18 14:58:16 +0200 | [diff] [blame] | 85 | |
| 86 | #if defined(CONFIG_OF_BOARD) |
| 87 | void *board_fdt_blob_setup(void) |
| 88 | { |
| 89 | static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR; |
| 90 | |
| 91 | if (fdt_magic(fw_dtb) != FDT_MAGIC) { |
| 92 | printf("DTB is not passed via %llx\n", (u64)fw_dtb); |
| 93 | return NULL; |
| 94 | } |
| 95 | |
| 96 | return fw_dtb; |
| 97 | } |
| 98 | #endif |