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Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +09001/*
2 * board/renesas/salvator-x/salvator-x.c
Marek Vasut237dadd2017-05-13 15:57:53 +02003 * This file is Salvator-X/Salvator-XS board support.
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +09004 *
Marek Vasut5abb39b2017-05-13 15:57:46 +02005 * Copyright (C) 2015-2017 Renesas Electronics Corporation
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +09006 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <malloc.h>
13#include <netdev.h>
14#include <dm.h>
15#include <dm/platform_data/serial_sh.h>
16#include <asm/processor.h>
17#include <asm/mach-types.h>
18#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090019#include <linux/errno.h>
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090020#include <asm/arch/sys_proto.h>
21#include <asm/gpio.h>
22#include <asm/arch/gpio.h>
23#include <asm/arch/rmobile.h>
24#include <asm/arch/rcar-mstp.h>
Marek Vasut5abb39b2017-05-13 15:57:46 +020025#include <asm/arch/sh_sdhi.h>
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090026#include <i2c.h>
27#include <mmc.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define CPGWPCR 0xE6150904
32#define CPGWPR 0xE615090C
33
34#define CLK2MHZ(clk) (clk / 1000 / 1000)
35void s_init(void)
36{
37 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
38 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
39
40 /* Watchdog init */
41 writel(0xA5A5A500, &rwdt->rwtcsra);
42 writel(0xA5A5A500, &swdt->swtcsra);
43
44 writel(0xA5A50000, CPGWPCR);
45 writel(0xFFFFFFFF, CPGWPR);
46}
47
Marek Vasut3614d302017-05-13 15:57:41 +020048#define GSX_MSTP112 BIT(12) /* 3DG */
49#define TMU0_MSTP125 BIT(25) /* secure */
50#define TMU1_MSTP124 BIT(24) /* non-secure */
51#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
Marek Vasut51e80062017-05-13 15:57:47 +020052#define ETHERAVB_MSTP812 BIT(12)
Marek Vasutc16ed0b2017-05-13 15:57:48 +020053#define DVFS_MSTP926 BIT(26)
Marek Vasut5abb39b2017-05-13 15:57:46 +020054#define SD0_MSTP314 BIT(14)
55#define SD1_MSTP313 BIT(13)
56#define SD2_MSTP312 BIT(12) /* either MMC0 */
57#define SD3_MSTP311 BIT(11) /* either MMC1 */
58
59#define SD0CKCR 0xE6150074
60#define SD1CKCR 0xE6150078
61#define SD2CKCR 0xE6150268
62#define SD3CKCR 0xE615026C
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090063
64int board_early_init_f(void)
65{
66 /* TMU0,1 */ /* which use ? */
67 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
68 /* SCIF2 */
69 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
Marek Vasut51e80062017-05-13 15:57:47 +020070 /* EHTERAVB */
71 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
Marek Vasut5abb39b2017-05-13 15:57:46 +020072 /* eMMC */
73 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
74 /* SDHI0, 3 */
75 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
76
77 writel(0, SD0CKCR);
78 writel(0, SD1CKCR);
79 writel(0, SD2CKCR);
80 writel(0, SD3CKCR);
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090081
Marek Vasutc16ed0b2017-05-13 15:57:48 +020082#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
83 /* DVFS for reset */
84 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
85#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090086 return 0;
87}
88
89/* SYSC */
90/* R/- 32 Power status register 2(3DG) */
91#define SYSC_PWRSR2 0xE6180100
92/* -/W 32 Power resume control register 2 (3DG) */
93#define SYSC_PWRONCR2 0xE618010C
94
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090095int board_init(void)
96{
97 /* adress of boot parameters */
98 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
99
100 /* Init PFC controller */
Marek Vasut237dadd2017-05-13 15:57:53 +0200101#if defined(CONFIG_R8A7795)
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900102 r8a7795_pinmux_init();
Marek Vasut237dadd2017-05-13 15:57:53 +0200103#elif defined(CONFIG_R8A7796)
104 r8a7796_pinmux_init();
105#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900106
Marek Vasut237dadd2017-05-13 15:57:53 +0200107#if defined(CONFIG_R8A7795)
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900108 /* GSX: force power and clock supply */
109 writel(0x0000001F, SYSC_PWRONCR2);
110 while (readl(SYSC_PWRSR2) != 0x000003E0)
111 mdelay(20);
112
113 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
Marek Vasut237dadd2017-05-13 15:57:53 +0200114#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900115
Marek Vasut4659a622017-05-13 15:57:49 +0200116 /* USB1 pull-up */
117 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
118
Marek Vasut6b1bcd12017-08-28 14:12:34 +0200119#ifdef CONFIG_RENESAS_RAVB
Marek Vasut51e80062017-05-13 15:57:47 +0200120 /* EtherAVB Enable */
121 /* GPSR2 */
122 gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
123 gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
124 gpio_request(GPIO_GFN_AVB_LINK, NULL);
125 gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
126 gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
127 gpio_request(GPIO_GFN_AVB_MDC, NULL);
128
129 /* IPSR0 */
130 gpio_request(GPIO_IFN_AVB_MDC, NULL);
131 gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
132 gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
133 gpio_request(GPIO_IFN_AVB_LINK, NULL);
134 gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
135 gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
136 /* IPSR1 */
137 gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
138 /* IPSR2 */
139 gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
140 /* IPSR3 */
141 gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
142
Marek Vasut237dadd2017-05-13 15:57:53 +0200143#if defined(CONFIG_R8A7795)
Marek Vasut4659a622017-05-13 15:57:49 +0200144 /* USB2_OVC */
145 gpio_request(GPIO_GP_6_15, NULL);
146 gpio_direction_input(GPIO_GP_6_15);
147
148 /* USB2_PWEN */
149 gpio_request(GPIO_GP_6_14, NULL);
150 gpio_direction_output(GPIO_GP_6_14, 1);
151 gpio_set_value(GPIO_GP_6_14, 1);
Marek Vasut237dadd2017-05-13 15:57:53 +0200152#endif
Marek Vasut51e80062017-05-13 15:57:47 +0200153 /* AVB_PHY_RST */
154 gpio_request(GPIO_GP_2_10, NULL);
155 gpio_direction_output(GPIO_GP_2_10, 0);
156 mdelay(20);
157 gpio_set_value(GPIO_GP_2_10, 1);
158 udelay(1);
159#endif
160
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900161 return 0;
162}
Marek Vasut5abb39b2017-05-13 15:57:46 +0200163
164#ifdef CONFIG_SH_SDHI
165int board_mmc_init(bd_t *bis)
166{
Marek Vasut5abb39b2017-05-13 15:57:46 +0200167 /* SDHI0 */
168 gpio_request(GPIO_GFN_SD0_DAT0, NULL);
169 gpio_request(GPIO_GFN_SD0_DAT1, NULL);
170 gpio_request(GPIO_GFN_SD0_DAT2, NULL);
171 gpio_request(GPIO_GFN_SD0_DAT3, NULL);
172 gpio_request(GPIO_GFN_SD0_CLK, NULL);
173 gpio_request(GPIO_GFN_SD0_CMD, NULL);
174 gpio_request(GPIO_GFN_SD0_CD, NULL);
175 gpio_request(GPIO_GFN_SD0_WP, NULL);
176
177 gpio_request(GPIO_GP_5_2, NULL);
178 gpio_request(GPIO_GP_5_1, NULL);
179 gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
180 gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
181
Marek Vasut5abb39b2017-05-13 15:57:46 +0200182 /* SDHI1/SDHI2 eMMC */
183 gpio_request(GPIO_GFN_SD1_DAT0, NULL);
184 gpio_request(GPIO_GFN_SD1_DAT1, NULL);
185 gpio_request(GPIO_GFN_SD1_DAT2, NULL);
186 gpio_request(GPIO_GFN_SD1_DAT3, NULL);
187 gpio_request(GPIO_GFN_SD2_DAT0, NULL);
188 gpio_request(GPIO_GFN_SD2_DAT1, NULL);
189 gpio_request(GPIO_GFN_SD2_DAT2, NULL);
190 gpio_request(GPIO_GFN_SD2_DAT3, NULL);
191 gpio_request(GPIO_GFN_SD2_CLK, NULL);
Marek Vasut237dadd2017-05-13 15:57:53 +0200192#if defined(CONFIG_R8A7795)
Marek Vasut5abb39b2017-05-13 15:57:46 +0200193 gpio_request(GPIO_GFN_SD2_CMD, NULL);
Marek Vasut237dadd2017-05-13 15:57:53 +0200194#elif defined(CONFIG_R8A7796)
195 gpio_request(GPIO_FN_SD2_CMD, NULL);
196#else
197#error Only R8A7795 and R87796 is supported
198#endif
Marek Vasut5abb39b2017-05-13 15:57:46 +0200199 gpio_request(GPIO_GP_5_3, NULL);
200 gpio_request(GPIO_GP_5_9, NULL);
201 gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
202 gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
203
Marek Vasut237dadd2017-05-13 15:57:53 +0200204#if defined(CONFIG_R8A7795)
Marek Vasut5abb39b2017-05-13 15:57:46 +0200205 /* SDHI3 */
206 gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
207 gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
208 gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
209 gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
210 gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
211 gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
Marek Vasut237dadd2017-05-13 15:57:53 +0200212#elif defined(CONFIG_R8A7796)
213 gpio_request(GPIO_FN_SD3_DAT0, NULL); /* GP_4_9 */
214 gpio_request(GPIO_FN_SD3_DAT1, NULL); /* GP_4_10 */
215 gpio_request(GPIO_FN_SD3_DAT2, NULL); /* GP_4_11 */
216 gpio_request(GPIO_FN_SD3_DAT3, NULL); /* GP_4_12 */
217 gpio_request(GPIO_FN_SD3_CLK, NULL); /* GP_4_7 */
218 gpio_request(GPIO_FN_SD3_CMD, NULL); /* GP_4_8 */
219#else
220#error Only R8A7795 and R87796 is supported
221#endif
Marek Vasut5abb39b2017-05-13 15:57:46 +0200222 /* IPSR10 */
223 gpio_request(GPIO_FN_SD3_CD, NULL);
224 gpio_request(GPIO_FN_SD3_WP, NULL);
225
226 gpio_request(GPIO_GP_3_15, NULL);
227 gpio_request(GPIO_GP_3_14, NULL);
228 gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
229 gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
230
Marek Vasutc9afcf62017-08-20 17:13:47 +0200231 return 0;
Marek Vasut5abb39b2017-05-13 15:57:46 +0200232}
233#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900234
235int dram_init(void)
236{
Marek Vasut3fca9d22017-05-13 15:57:50 +0200237 gd->ram_size = PHYS_SDRAM_1_SIZE;
238#if (CONFIG_NR_DRAM_BANKS >= 2)
239 gd->ram_size += PHYS_SDRAM_2_SIZE;
240#endif
241#if (CONFIG_NR_DRAM_BANKS >= 3)
242 gd->ram_size += PHYS_SDRAM_3_SIZE;
243#endif
244#if (CONFIG_NR_DRAM_BANKS >= 4)
245 gd->ram_size += PHYS_SDRAM_4_SIZE;
246#endif
247
248 return 0;
249}
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900250
Marek Vasut3fca9d22017-05-13 15:57:50 +0200251int dram_init_banksize(void)
252{
253 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
254 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
255#if (CONFIG_NR_DRAM_BANKS >= 2)
256 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
257 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
258#endif
259#if (CONFIG_NR_DRAM_BANKS >= 3)
260 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
261 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
262#endif
263#if (CONFIG_NR_DRAM_BANKS >= 4)
264 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
265 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
266#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900267 return 0;
268}
269
270const struct rmobile_sysinfo sysinfo = {
271 CONFIG_RCAR_BOARD_STRING
272};
273
274#define RST_BASE 0xE6160000
275#define RST_CA57RESCNT (RST_BASE + 0x40)
276#define RST_CA53RESCNT (RST_BASE + 0x44)
277#define RST_RSTOUTCR (RST_BASE + 0x58)
278#define RST_CODE 0xA5A5000F
279
280void reset_cpu(ulong addr)
281{
Marek Vasutc16ed0b2017-05-13 15:57:48 +0200282#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
283 i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
284#else
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900285 /* only CA57 ? */
286 writel(RST_CODE, RST_CA57RESCNT);
Marek Vasutc16ed0b2017-05-13 15:57:48 +0200287#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900288}