Manivannan Sadhasivam | cf33f92 | 2019-08-02 20:40:09 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2019 Linaro |
| 4 | * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 8 | #include <cpu_func.h> |
Manivannan Sadhasivam | cf33f92 | 2019-08-02 20:40:09 +0530 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | #include <errno.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 11 | #include <asm/cache.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 12 | #include <init.h> |
Manivannan Sadhasivam | cf33f92 | 2019-08-02 20:40:09 +0530 | [diff] [blame] | 13 | #include <asm/io.h> |
| 14 | #include <asm/arch/hi3660.h> |
| 15 | #include <asm/armv8/mmu.h> |
| 16 | #include <asm/psci.h> |
| 17 | #include <linux/arm-smccc.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 18 | #include <linux/delay.h> |
Manivannan Sadhasivam | cf33f92 | 2019-08-02 20:40:09 +0530 | [diff] [blame] | 19 | #include <linux/psci.h> |
| 20 | |
| 21 | #define PMIC_REG_TO_BUS_ADDR(x) (x << 2) |
| 22 | #define PMIC_VSEL_MASK 0x7 |
| 23 | |
| 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
| 26 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
| 27 | #include <dm/platform_data/serial_pl01x.h> |
| 28 | |
| 29 | static const struct pl01x_serial_platdata serial_platdata = { |
| 30 | .base = HI3660_UART6_BASE, |
| 31 | .type = TYPE_PL011, |
| 32 | .clock = 19200000 |
| 33 | }; |
| 34 | |
| 35 | U_BOOT_DEVICE(hikey960_serial0) = { |
| 36 | .name = "serial_pl01x", |
| 37 | .platdata = &serial_platdata, |
| 38 | }; |
| 39 | #endif |
| 40 | |
| 41 | static struct mm_region hikey_mem_map[] = { |
| 42 | { |
| 43 | .virt = 0x0UL, /* DDR */ |
| 44 | .phys = 0x0UL, |
| 45 | .size = 0xC0000000UL, |
| 46 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 47 | PTE_BLOCK_INNER_SHARE |
| 48 | }, { |
| 49 | .virt = 0xE0000000UL, /* Peripheral block */ |
| 50 | .phys = 0xE0000000UL, |
| 51 | .size = 0x20000000UL, |
| 52 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 53 | PTE_BLOCK_NON_SHARE | |
| 54 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 55 | }, { |
| 56 | /* List terminator */ |
| 57 | 0, |
| 58 | } |
| 59 | }; |
| 60 | |
| 61 | struct mm_region *mem_map = hikey_mem_map; |
| 62 | |
| 63 | int board_early_init_f(void) |
| 64 | { |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | int misc_init_r(void) |
| 69 | { |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | int dram_init(void) |
| 74 | { |
| 75 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | int dram_init_banksize(void) |
| 81 | { |
| 82 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 83 | gd->bd->bi_dram[0].size = gd->ram_size; |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | void hikey960_sd_init(void) |
| 89 | { |
| 90 | u32 data; |
| 91 | |
| 92 | /* Enable FPLL0 */ |
| 93 | data = readl(SCTRL_SCFPLLCTRL0); |
| 94 | data |= SCTRL_SCFPLLCTRL0_FPLL0_EN; |
| 95 | writel(data, SCTRL_SCFPLLCTRL0); |
| 96 | |
| 97 | /* Configure LDO16 */ |
| 98 | data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) & |
| 99 | PMIC_VSEL_MASK; |
| 100 | data |= 6; |
| 101 | writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)); |
| 102 | |
| 103 | data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78)); |
| 104 | data |= 2; |
| 105 | writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78)); |
| 106 | |
| 107 | udelay(100); |
| 108 | |
| 109 | /* Configure LDO9 */ |
| 110 | data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) & |
| 111 | PMIC_VSEL_MASK; |
| 112 | data |= 5; |
| 113 | writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)); |
| 114 | |
| 115 | data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a)); |
| 116 | data |= 2; |
| 117 | writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a)); |
| 118 | |
| 119 | udelay(100); |
| 120 | |
| 121 | /* GPIO CD */ |
| 122 | writel(0, PINMUX4_SDDET); |
| 123 | |
| 124 | /* SD Pinconf */ |
| 125 | writel(15 << 4, PINCONF3_SDCLK); |
| 126 | writel((1 << 0) | (8 << 4), PINCONF3_SDCMD); |
| 127 | writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0); |
| 128 | writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1); |
| 129 | writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2); |
| 130 | writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3); |
| 131 | |
| 132 | /* Set SD clock mux */ |
| 133 | do { |
| 134 | data = readl(CRG_REG_BASE + 0xb8); |
| 135 | data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16)); |
| 136 | writel(data, CRG_REG_BASE + 0xb8); |
| 137 | |
| 138 | data = readl(CRG_REG_BASE + 0xb8); |
| 139 | } while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4))); |
| 140 | |
| 141 | /* Take SD out of reset */ |
| 142 | writel(1 << 18, CRG_PERRSTDIS4); |
| 143 | do { |
| 144 | data = readl(CRG_PERRSTSTAT4); |
| 145 | } while ((data & (1 << 18)) == (1 << 18)); |
| 146 | |
| 147 | /* Enable hclk_gate_sd */ |
| 148 | data = readl(CRG_REG_BASE + 0); |
| 149 | data |= (1 << 30); |
| 150 | writel(data, CRG_REG_BASE + 0); |
| 151 | |
| 152 | /* Enable clk_andgt_mmc */ |
| 153 | data = readl(CRG_REG_BASE + 0xf4); |
| 154 | data |= ((1 << 3) | (1 << 3 << 16)); |
| 155 | writel(data, CRG_REG_BASE + 0xf4); |
| 156 | |
| 157 | /* Enable clk_gate_sd */ |
| 158 | data = readl(CRG_PEREN4); |
| 159 | data |= (1 << 17); |
| 160 | writel(data, CRG_PEREN4); |
| 161 | do { |
| 162 | data = readl(CRG_PERCLKEN4); |
| 163 | } while ((data & (1 << 17)) != (1 << 17)); |
| 164 | } |
| 165 | |
| 166 | static void show_psci_version(void) |
| 167 | { |
| 168 | struct arm_smccc_res res; |
| 169 | |
| 170 | arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); |
| 171 | |
| 172 | printf("PSCI: v%ld.%ld\n", |
| 173 | PSCI_VERSION_MAJOR(res.a0), |
| 174 | PSCI_VERSION_MINOR(res.a0)); |
| 175 | } |
| 176 | |
| 177 | int board_init(void) |
| 178 | { |
| 179 | /* Init SD */ |
| 180 | hikey960_sd_init(); |
| 181 | |
| 182 | show_psci_version(); |
| 183 | |
| 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | void reset_cpu(ulong addr) |
| 188 | { |
| 189 | psci_system_reset(); |
| 190 | } |