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git01.mediatek.com / filogic / uboot / 6abdf01ad9f2441743b4f056f381d7ea9dd12c6a / . / arch / x86 / lib / fsp2 / fsp_meminit.c
blob: ce0b0aff76beda38344ad1712a423534fa1f0d7e [file] [log] [blame]
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]1// SPDX-License-Identifier: Intel
2/*
3 * Copyright (C) 2015-2016 Intel Corp.
4 * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
5 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
6 * Mostly taken from coreboot fsp2_0/memory_init.c
7 */
8
9#include <common.h>
10#include <binman.h>
Simon Glass1ea97892020-05-10 11:40:00 -0600[diff] [blame]11#include <bootstage.h>
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]12#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]13#include <log.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]14#include <asm/mrccache.h>
15#include <asm/fsp/fsp_infoheader.h>
16#include <asm/fsp2/fsp_api.h>
17#include <asm/fsp2/fsp_internal.h>
18#include <asm/arch/fsp/fsp_configs.h>
19#include <asm/arch/fsp/fsp_m_upd.h>
20
21static int prepare_mrc_cache_type(enum mrc_type_t type,
22 struct mrc_data_container **cachep)
23{
24 struct mrc_data_container *cache;
25 struct mrc_region entry;
26 int ret;
27
28 ret = mrccache_get_region(type, NULL, &entry);
29 if (ret)
30 return ret;
31 cache = mrccache_find_current(&entry);
32 if (!cache)
33 return -ENOENT;
34
35 log_debug("MRC at %x, size %x\n", (uint)cache->data, cache->data_size);
36 *cachep = cache;
37
38 return 0;
39}
40
41int prepare_mrc_cache(struct fspm_upd *upd)
42{
43 struct mrc_data_container *cache;
44 int ret;
45
46 ret = prepare_mrc_cache_type(MRC_TYPE_NORMAL, &cache);
47 if (ret)
48 return log_msg_ret("Cannot get normal cache", ret);
49 upd->arch.nvs_buffer_ptr = cache->data;
50
51 ret = prepare_mrc_cache_type(MRC_TYPE_VAR, &cache);
52 if (ret)
53 return log_msg_ret("Cannot get var cache", ret);
54 upd->config.variable_nvs_buffer_ptr = cache->data;
55
56 return 0;
57}
58
59int fsp_memory_init(bool s3wake, bool use_spi_flash)
60{
61 struct fspm_upd upd, *fsp_upd;
62 fsp_memory_init_func func;
63 struct binman_entry entry;
64 struct fsp_header *hdr;
65 struct hob_header *hob;
66 struct udevice *dev;
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]67 int delay;
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]68 int ret;
69
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]70 log_debug("Locating FSP\n");
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]71 ret = fsp_locate_fsp(FSP_M, &entry, use_spi_flash, &dev, &hdr, NULL);
72 if (ret)
73 return log_msg_ret("locate FSP", ret);
74 debug("Found FSP_M at %x, size %x\n", hdr->img_base, hdr->img_size);
75
76 /* Copy over the default config */
77 fsp_upd = (struct fspm_upd *)(hdr->img_base + hdr->cfg_region_off);
78 if (fsp_upd->header.signature != FSPM_UPD_SIGNATURE)
79 return log_msg_ret("Bad UPD signature", -EPERM);
80 memcpy(&upd, fsp_upd, sizeof(upd));
81
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]82 delay = dev_read_u32_default(dev, "fspm,training-delay", 0);
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]83 ret = fspm_update_config(dev, &upd);
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]84 if (ret) {
85 if (ret != -ENOENT)
86 return log_msg_ret("Could not setup config", ret);
87 } else {
88 delay = 0;
89 }
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]90
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]91 if (delay)
92 printf("SDRAM training (%d seconds)...", delay);
93 else
94 log_debug("SDRAM init...");
Simon Glassea6a6092020-05-10 11:39:59 -0600[diff] [blame]95 bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_M, "fsp-m");
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]96 func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init);
97 ret = func(&upd, &hob);
Simon Glassea6a6092020-05-10 11:39:59 -0600[diff] [blame]98 bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M);
Simon Glassc5c4ed62020-07-02 21:12:12 -0600[diff] [blame]99 cpu_reinit_fpu();
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]100 if (delay)
101 printf("done\n");
102 else
103 log_debug("done\n");
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]104 if (ret)
105 return log_msg_ret("SDRAM init fail\n", ret);
106
107 gd->arch.hob_list = hob;
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]108
109 ret = fspm_done(dev);
110 if (ret)
111 return log_msg_ret("fsm_done\n", ret);
112
113 return 0;
114}