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Mark Kettenisc9329762021-11-02 18:21:57 +01001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Apple GPIO controller
8
9maintainers:
10 - Mark Kettenis <kettenis@openbsd.org>
11
12description: |
13 The Apple GPIO controller is a simple combined pin and GPIO
14 controller present on Apple ARM SoC platforms, including various
15 iPhone and iPad devices and the "Apple Silicon" Macs.
16
17properties:
18 compatible:
19 items:
20 - const: apple,t8103-pinctrl
21 - const: apple,pinctrl
22
23 reg:
24 maxItems: 1
25
26 clocks:
27 maxItems: 1
28
29 gpio-controller: true
30
31 '#gpio-cells':
32 const: 2
33
34 gpio-ranges:
35 maxItems: 1
36
37 interrupts:
38 description: One interrupt for each of the (up to 7) interrupt
39 groups supported by the controller sorted by interrupt group
40 number in ascending order.
41 minItems: 1
42 maxItems: 7
43
44 interrupt-controller: true
45
46patternProperties:
47 '-pins$':
48 type: object
49 $ref: pinmux-node.yaml#
50
51 properties:
52 pinmux:
53 description:
54 Values are constructed from pin number and alternate function
55 configuration number using the APPLE_PINMUX() helper macro
56 defined in include/dt-bindings/pinctrl/apple.h.
57
58 required:
59 - pinmux
60
61 additionalProperties: false
62
63required:
64 - compatible
65 - reg
66 - gpio-controller
67 - '#gpio-cells'
68 - gpio-ranges
69
70additionalProperties: false
71
72examples:
73 - |
74 #include <dt-bindings/interrupt-controller/apple-aic.h>
75 #include <dt-bindings/pinctrl/apple.h>
76
77 soc {
78 #address-cells = <2>;
79 #size-cells = <2>;
80
81 pinctrl: pinctrl@23c100000 {
82 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
83 reg = <0x2 0x3c100000 0x0 0x100000>;
84 clocks = <&gpio_clk>;
85
86 gpio-controller;
87 #gpio-cells = <2>;
88 gpio-ranges = <&pinctrl 0 0 212>;
89
90 interrupt-controller;
91 interrupt-parent = <&aic>;
92 interrupts = <AIC_IRQ 16 IRQ_TYPE_LEVEL_HIGH>,
93 <AIC_IRQ 17 IRQ_TYPE_LEVEL_HIGH>,
94 <AIC_IRQ 18 IRQ_TYPE_LEVEL_HIGH>,
95 <AIC_IRQ 19 IRQ_TYPE_LEVEL_HIGH>,
96 <AIC_IRQ 20 IRQ_TYPE_LEVEL_HIGH>,
97 <AIC_IRQ 21 IRQ_TYPE_LEVEL_HIGH>,
98 <AIC_IRQ 22 IRQ_TYPE_LEVEL_HIGH>;
99
100 pcie_pins: pcie-pins {
101 pinmux = <APPLE_PINMUX(150, 1)>,
102 <APPLE_PINMUX(151, 1)>,
103 <APPLE_PINMUX(32, 1)>;
104 };
105 };
106 };