Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 6a6b4f55cdb4e0fa9463bf623568cea65d823d97 / . / configs / orangepi-rk3399_defconfig
blob: 337eeab8b42bd2521b157d6565eb6667cdc8df8d [file] [log] [blame]
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]5CONFIG_NR_DRAM_BANKS=1
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]6CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]7CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]8CONFIG_ROCKCHIP_RK3399=y
Kever Yang1b662092020-02-19 17:51:07 +0800[diff] [blame]9CONFIG_TARGET_EVB_RK3399=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]10CONFIG_DEBUG_UART_BASE=0xFF1A0000
11CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]12CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]13CONFIG_DEBUG_UART=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]14CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]15CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]16CONFIG_SPL_MAX_SIZE=0x2e000
17CONFIG_SPL_PAD_TO=0x7f8000
Kever Yang20673542019-08-20 11:47:02 +0800[diff] [blame]18# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Quentin Schulz95edee72023-06-21 18:02:52 +0200[diff] [blame]19CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
Jagan Teki4d88eea2019-05-29 13:55:47 +0530[diff] [blame]20CONFIG_TPL=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]21CONFIG_CMD_BOOTZ=y
22CONFIG_CMD_GPT=y
23CONFIG_CMD_MMC=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]24CONFIG_CMD_USB=y
25# CONFIG_CMD_SETEXPR is not set
26CONFIG_CMD_TIME=y
27CONFIG_SPL_OF_CONTROL=y
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame^]28CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]29CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]30CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]31CONFIG_ROCKCHIP_GPIO=y
32CONFIG_SYS_I2C_ROCKCHIP=y
33CONFIG_MMC_DW=y
34CONFIG_MMC_DW_ROCKCHIP=y
35CONFIG_MMC_SDHCI=y
36CONFIG_MMC_SDHCI_ROCKCHIP=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]37CONFIG_ETH_DESIGNWARE=y
38CONFIG_GMAC_ROCKCHIP=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]39CONFIG_PMIC_RK8XX=y
40CONFIG_REGULATOR_PWM=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]41CONFIG_REGULATOR_RK8XX=y
42CONFIG_PWM_ROCKCHIP=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]43CONFIG_BAUDRATE=1500000
44CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]45CONFIG_SYS_NS16550_MEM32=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]46CONFIG_SYSRESET=y
47CONFIG_USB=y
48CONFIG_USB_XHCI_HCD=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]49CONFIG_USB_EHCI_HCD=y
50CONFIG_USB_EHCI_GENERIC=y
Jonas Karlmanac8d1572023-11-12 17:48:57 +0000[diff] [blame]51CONFIG_USB_DWC3=y
52CONFIG_USB_DWC3_GENERIC=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]53CONFIG_USB_HOST_ETHER=y
54CONFIG_USB_ETHER_ASIX=y
55CONFIG_USB_ETHER_ASIX88179=y
56CONFIG_USB_ETHER_MCS7830=y
57CONFIG_USB_ETHER_RTL8152=y
58CONFIG_USB_ETHER_SMSC95XX=y
Jagan Teki4d88eea2019-05-29 13:55:47 +0530[diff] [blame]59CONFIG_SPL_TINY_MEMSET=y
Jagan Tekib1fdce42019-03-11 13:50:04 +0530[diff] [blame]60CONFIG_ERRNO_STR=y