Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 2 | /** |
| 3 | * (C) Copyright 2014, Cavium Inc. |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 4 | **/ |
| 5 | |
| 6 | #ifndef __THUNDERX_88XX_H__ |
| 7 | #define __THUNDERX_88XX_H__ |
| 8 | |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 9 | #define MEM_BASE 0x00500000 |
| 10 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame^] | 11 | #define CFG_SYS_LOWMEM_BASE MEM_BASE |
Sergey Temerkhanov | 62dce24 | 2015-10-14 09:55:51 -0700 | [diff] [blame] | 12 | |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 13 | /* Link Definitions */ |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 14 | |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 15 | /* SMP Spin Table Definitions */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 16 | #define CPU_RELEASE_ADDR (CFG_SYS_SDRAM_BASE + 0x7fff0) |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 17 | |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 18 | /* PL011 Serial Configuration */ |
| 19 | |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 20 | #define CONFIG_PL011_CLOCK 24000000 |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 21 | |
| 22 | /* Generic Interrupt Controller Definitions */ |
| 23 | #define GICD_BASE (0x801000000000) |
| 24 | #define GICR_BASE (0x801000002000) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame^] | 25 | #define CFG_SYS_SERIAL0 0x87e024000000 |
| 26 | #define CFG_SYS_SERIAL1 0x87e025000000 |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 27 | |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 28 | /* Miscellaneous configurable options */ |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 29 | |
| 30 | /* Physical Memory Map */ |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 31 | #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ |
| 32 | #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 33 | #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 34 | |
| 35 | /* Initial environment variables */ |
| 36 | #define UBOOT_IMG_HEAD_SIZE 0x40 |
| 37 | /* C80000 - 0x40 */ |
| 38 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 39 | "kernel_addr=08007ffc0\0" \ |
| 40 | "fdt_addr=0x94C00000\0" \ |
| 41 | "fdt_high=0x9fffffff\0" |
| 42 | |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 43 | /* Do not preserve environment */ |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 44 | |
Sergey Temerkhanov | 69f7a03 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 45 | #define PLL_REF_CLK 50000000 /* 50 MHz */ |
| 46 | #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) |
| 47 | |
| 48 | #endif /* __THUNDERX_88XX_H__ */ |