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git01.mediatek.com / filogic / uboot / 6a5dccc02202c5bf334825ef3104f9d85c9cb678 / . / arch / m68k / include / asm / immap_5301x.h
blob: e1f7858b100762c90451cab521d84cc80f0fab9e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]2/*
3 * MCF5301x Internal Memory Map
4 *
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]7 */
8
9#ifndef __IMMAP_5301X__
10#define __IMMAP_5301X__
11
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame^]12#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000)
13#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000)
14#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000)
15#define MMAP_MPU (CFG_SYS_MBAR + 0x00014000)
16#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000)
17#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00034000)
18#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000)
19#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000)
20#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000)
21#define MMAP_INTC1 (CFG_SYS_MBAR + 0x0004C000)
22#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000)
23#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000)
24#define MMAP_DSPI (CFG_SYS_MBAR + 0x0005C000)
25#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000)
26#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000)
27#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000)
28#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000)
29#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000)
30#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000)
31#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000)
32#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000)
33#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000)
34#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00088000)
35#define MMAP_PIT3 (CFG_SYS_MBAR + 0x0008C000)
36#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00090000)
37#define MMAP_EPORT1 (CFG_SYS_MBAR + 0x00094000)
38#define MMAP_VOICOD (CFG_SYS_MBAR + 0x0009C000)
39#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000)
40#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004)
41#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000)
42#define MMAP_RTC (CFG_SYS_MBAR + 0x000A8000)
43#define MMAP_SIM (CFG_SYS_MBAR + 0x000AC000)
44#define MMAP_USBOTG (CFG_SYS_MBAR + 0x000B0000)
45#define MMAP_USBH (CFG_SYS_MBAR + 0x000B4000)
46#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000B8000)
47#define MMAP_SSI (CFG_SYS_MBAR + 0x000BC000)
48#define MMAP_PLL (CFG_SYS_MBAR + 0x000C0000)
49#define MMAP_RNG (CFG_SYS_MBAR + 0x000C4000)
50#define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000)
51#define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]52
53#include <asm/coldfire/crossbar.h>
54#include <asm/coldfire/dspi.h>
55#include <asm/coldfire/edma.h>
56#include <asm/coldfire/eport.h>
57#include <asm/coldfire/flexbus.h>
58#include <asm/coldfire/intctrl.h>
59#include <asm/coldfire/ssi.h>
60#include <asm/coldfire/rng.h>
61#include <asm/rtc.h>
62
63/* System Controller Module */
64typedef struct scm1 {
65 u32 mpr; /* 0x00 Master Privilege */
66 u32 rsvd1[7];
67 u32 pacra; /* 0x20 Peripheral Access Ctrl A */
68 u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
69 u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
70 u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
71 u32 rsvd2[4];
72 u32 pacre; /* 0x40 Peripheral Access Ctrl E */
73 u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
74 u32 pacrg; /* 0x48 Peripheral Access Ctrl G */
75} scm1_t;
76
77typedef struct scm2 {
78 u8 rsvd1[19]; /* 0x00 - 0x12 */
79 u8 wcr; /* 0x13 */
80 u16 rsvd2; /* 0x14 - 0x15 */
81 u16 cwcr; /* 0x16 */
82 u8 rsvd3[3]; /* 0x18 - 0x1A */
83 u8 cwsr; /* 0x1B */
84 u8 rsvd4[3]; /* 0x1C - 0x1E */
85 u8 scmisr; /* 0x1F */
86 u32 rsvd5; /* 0x20 - 0x23 */
87 u8 bcr; /* 0x24 */
88 u8 rsvd6[74]; /* 0x25 - 0x6F */
89 u32 cfadr; /* 0x70 */
90 u8 rsvd7; /* 0x74 */
91 u8 cfier; /* 0x75 */
92 u8 cfloc; /* 0x76 */
93 u8 cfatr; /* 0x77 */
94 u32 rsvd8; /* 0x78 - 0x7B */
95 u32 cfdtr; /* 0x7C */
96} scm2_t;
97
98/* PWM module */
99typedef struct pwm_ctrl {
100 u8 en; /* 0x00 PWM Enable */
101 u8 pol; /* 0x01 Polarity */
102 u8 clk; /* 0x02 Clock Select */
103 u8 prclk; /* 0x03 Prescale Clock Select */
104 u8 cae; /* 0x04 Center Align Enable */
105 u8 ctl; /* 0x05 Ctrl */
106 u8 res1[2]; /* 0x06 - 0x07 */
107 u8 scla; /* 0x08 Scale A */
108 u8 sclb; /* 0x09 Scale B */
109 u8 res2[2]; /* 0x0A - 0x0B */
110 u8 cnt0; /* 0x0C Channel 0 Counter */
111 u8 cnt1; /* 0x0D Channel 1 Counter */
112 u8 cnt2; /* 0x0E Channel 2 Counter */
113 u8 cnt3; /* 0x0F Channel 3 Counter */
114 u8 cnt4; /* 0x10 Channel 4 Counter */
115 u8 cnt5; /* 0x11 Channel 5 Counter */
116 u8 cnt6; /* 0x12 Channel 6 Counter */
117 u8 cnt7; /* 0x13 Channel 7 Counter */
118 u8 per0; /* 0x14 Channel 0 Period */
119 u8 per1; /* 0x15 Channel 1 Period */
120 u8 per2; /* 0x16 Channel 2 Period */
121 u8 per3; /* 0x17 Channel 3 Period */
122 u8 per4; /* 0x18 Channel 4 Period */
123 u8 per5; /* 0x19 Channel 5 Period */
124 u8 per6; /* 0x1A Channel 6 Period */
125 u8 per7; /* 0x1B Channel 7 Period */
126 u8 dty0; /* 0x1C Channel 0 Duty */
127 u8 dty1; /* 0x1D Channel 1 Duty */
128 u8 dty2; /* 0x1E Channel 2 Duty */
129 u8 dty3; /* 0x1F Channel 3 Duty */
130 u8 dty4; /* 0x20 Channel 4 Duty */
131 u8 dty5; /* 0x21 Channel 5 Duty */
132 u8 dty6; /* 0x22 Channel 6 Duty */
133 u8 dty7; /* 0x23 Channel 7 Duty */
134 u8 sdn; /* 0x24 Shutdown */
135 u8 res3[3]; /* 0x25 - 0x27 */
136} pwm_t;
137
138/* Chip configuration module */
139typedef struct rcm {
140 u8 rcr;
141 u8 rsr;
142} rcm_t;
143
144typedef struct ccm_ctrl {
145 u16 ccr; /* 0x00 Chip Cfg */
146 u16 res1; /* 0x02 */
147 u16 rcon; /* 0x04 Reset Cfg */
148 u16 cir; /* 0x06 Chip ID */
149 u32 res2; /* 0x08 */
150 u16 misccr; /* 0x0A Misc Ctrl */
151 u16 cdr; /* 0x0C Clock divider */
152 u16 uhcsr; /* 0x10 USB Host status */
153 u16 uocsr; /* 0x12 USB On-the-Go Status */
154 u16 res3; /* 0x14 */
155 u16 codeccr; /* 0x16 Codec Control */
156 u16 misccr2; /* 0x18 Misc2 Ctrl */
157} ccm_t;
158
159/* GPIO port */
160typedef struct gpio_ctrl {
161 /* Port Output Data */
162 u8 podr_fbctl; /* 0x00 */
163 u8 podr_be; /* 0x01 */
164 u8 podr_cs; /* 0x02 */
165 u8 podr_dspi; /* 0x03 */
166 u8 res01; /* 0x04 */
167 u8 podr_fec0; /* 0x05 */
168 u8 podr_feci2c; /* 0x06 */
169 u8 res02[2]; /* 0x07 - 0x08 */
170 u8 podr_simp1; /* 0x09 */
171 u8 podr_simp0; /* 0x0A */
172 u8 podr_timer; /* 0x0B */
173 u8 podr_uart; /* 0x0C */
174 u8 podr_debug; /* 0x0D */
175 u8 res03; /* 0x0E */
176 u8 podr_sdhc; /* 0x0F */
177 u8 podr_ssi; /* 0x10 */
178 u8 res04[3]; /* 0x11 - 0x13 */
179
180 /* Port Data Direction */
181 u8 pddr_fbctl; /* 0x14 */
182 u8 pddr_be; /* 0x15 */
183 u8 pddr_cs; /* 0x16 */
184 u8 pddr_dspi; /* 0x17 */
185 u8 res05; /* 0x18 */
186 u8 pddr_fec0; /* 0x19 */
187 u8 pddr_feci2c; /* 0x1A */
188 u8 res06[2]; /* 0x1B - 0x1C */
189 u8 pddr_simp1; /* 0x1D */
190 u8 pddr_simp0; /* 0x1E */
191 u8 pddr_timer; /* 0x1F */
192 u8 pddr_uart; /* 0x20 */
193 u8 pddr_debug; /* 0x21 */
194 u8 res07; /* 0x22 */
195 u8 pddr_sdhc; /* 0x23 */
196 u8 pddr_ssi; /* 0x24 */
197 u8 res08[3]; /* 0x25 - 0x27 */
198
199 /* Port Data Direction */
200 u8 ppdr_fbctl; /* 0x28 */
201 u8 ppdr_be; /* 0x29 */
202 u8 ppdr_cs; /* 0x2A */
203 u8 ppdr_dspi; /* 0x2B */
204 u8 res09; /* 0x2C */
205 u8 ppdr_fec0; /* 0x2D */
206 u8 ppdr_feci2c; /* 0x2E */
207 u8 res10[2]; /* 0x2F - 0x30 */
208 u8 ppdr_simp1; /* 0x31 */
209 u8 ppdr_simp0; /* 0x32 */
210 u8 ppdr_timer; /* 0x33 */
211 u8 ppdr_uart; /* 0x34 */
212 u8 ppdr_debug; /* 0x35 */
213 u8 res11; /* 0x36 */
214 u8 ppdr_sdhc; /* 0x37 */
215 u8 ppdr_ssi; /* 0x38 */
216 u8 res12[3]; /* 0x39 - 0x3B */
217
218 /* Port Clear Output Data */
219 u8 pclrr_fbctl; /* 0x3C */
220 u8 pclrr_be; /* 0x3D */
221 u8 pclrr_cs; /* 0x3E */
222 u8 pclrr_dspi; /* 0x3F */
223 u8 res13; /* 0x40 */
224 u8 pclrr_fec0; /* 0x41 */
225 u8 pclrr_feci2c; /* 0x42 */
226 u8 res14[2]; /* 0x43 - 0x44 */
227 u8 pclrr_simp1; /* 0x45 */
228 u8 pclrr_simp0; /* 0x46 */
229 u8 pclrr_timer; /* 0x47 */
230 u8 pclrr_uart; /* 0x48 */
231 u8 pclrr_debug; /* 0x49 */
232 u8 res15; /* 0x4A */
233 u8 pclrr_sdhc; /* 0x4B */
234 u8 pclrr_ssi; /* 0x4C */
235 u8 res16[3]; /* 0x4D - 0x4F */
236
237 /* Pin Assignment */
238 u8 par_fbctl; /* 0x50 */
239 u8 par_be; /* 0x51 */
240 u8 par_cs; /* 0x52 */
241 u8 res17; /* 0x53 */
242 u8 par_dspih; /* 0x54 */
243 u8 par_dspil; /* 0x55 */
244 u8 par_fec; /* 0x56 */
245 u8 par_feci2c; /* 0x57 */
246 u8 par_irq0h; /* 0x58 */
247 u8 par_irq0l; /* 0x59 */
248 u8 par_irq1h; /* 0x5A */
249 u8 par_irq1l; /* 0x5B */
250 u8 par_simp1h; /* 0x5C */
251 u8 par_simp1l; /* 0x5D */
252 u8 par_simp0; /* 0x5E */
253 u8 par_timer; /* 0x5F */
254 u8 par_uart; /* 0x60 */
255 u8 res18; /* 0x61 */
256 u8 par_debug; /* 0x62 */
257 u8 par_sdhc; /* 0x63 */
258 u8 par_ssih; /* 0x64 */
259 u8 par_ssil; /* 0x65 */
260 u8 res19[2]; /* 0x66 - 0x67 */
261
262 /* Mode Select Control */
263 /* Drive Strength Control */
264 u8 mscr_mscr1; /* 0x68 */
265 u8 mscr_mscr2; /* 0x69 */
266 u8 mscr_mscr3; /* 0x6A */
267 u8 mscr_mscr45; /* 0x6B */
268 u8 srcr_dspi; /* 0x6C */
269 u8 dscr_fec; /* 0x6D */
270 u8 srcr_i2c; /* 0x6E */
271 u8 srcr_irq; /* 0x6F */
272
273 u8 srcr_sim; /* 0x70 */
274 u8 srcr_timer; /* 0x71 */
275 u8 srcr_uart; /* 0x72 */
276 u8 res20; /* 0x73 */
277 u8 srcr_sdhc; /* 0x74 */
278 u8 srcr_ssi; /* 0x75 */
279 u8 res21[2]; /* 0x76 - 0x77 */
280 u8 pcr_pcrh; /* 0x78 */
281 u8 pcr_pcrl; /* 0x79 */
282} gpio_t;
283
284/* SDRAM controller */
285typedef struct sdram_ctrl {
286 u32 mode; /* 0x00 Mode/Extended Mode */
287 u32 ctrl; /* 0x04 Ctrl */
288 u32 cfg1; /* 0x08 Cfg 1 */
289 u32 cfg2; /* 0x0C Cfg 2 */
290 u32 res1[64]; /* 0x10 - 0x10F */
291 u32 cs0; /* 0x110 Chip Select 0 Cfg */
292 u32 cs1; /* 0x114 Chip Select 1 Cfg */
293} sdram_t;
294
295/* Clock Module */
296typedef struct pll_ctrl {
297 u32 pcr; /* 0x00 Ctrl */
298 u32 pdr; /* 0x04 Divider */
299 u32 psr; /* 0x08 Status */
300} pll_t;
301
302typedef struct rtcex {
303 u32 rsvd1[3];
304 u32 gocu;
305 u32 gocl;
306} rtcex_t;
307#endif /* __IMMAP_5301X__ */