Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010 |
| 4 | * Reinhard Meyer, reinhard.meyer@emk-elektronik.de |
| 5 | * (C) Copyright 2009 |
| 6 | * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
| 7 | * (C) Copyright 2013 |
| 8 | * Bo Shen <voice.shen@atmel.com> |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 12 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | f5c208d | 2019-11-14 12:57:20 -0700 | [diff] [blame] | 14 | #include <vsprintf.h> |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 15 | #include <asm/io.h> |
| 16 | #include <asm/arch/hardware.h> |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 17 | #include <asm/arch/at91_pit.h> |
| 18 | #include <asm/arch/at91_gpbr.h> |
| 19 | #include <asm/arch/clk.h> |
| 20 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame^] | 21 | #ifndef CFG_SYS_AT91_MAIN_CLOCK |
| 22 | #define CFG_SYS_AT91_MAIN_CLOCK 0 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 23 | #endif |
| 24 | |
| 25 | int arch_cpu_init(void) |
| 26 | { |
Nicolas Ferre | 6cb1af7 | 2020-11-11 13:15:08 +0200 | [diff] [blame] | 27 | #if defined(CONFIG_CLK_CCF) |
| 28 | return 0; |
| 29 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame^] | 30 | return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); |
Nicolas Ferre | 6cb1af7 | 2020-11-11 13:15:08 +0200 | [diff] [blame] | 31 | #endif |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 32 | } |
| 33 | |
| 34 | void arch_preboot_os(void) |
| 35 | { |
Eugen Hristev | be6a85f | 2020-08-20 16:11:52 +0300 | [diff] [blame] | 36 | #if (IS_ENABLED(CONFIG_ATMEL_PIT_TIMER)) |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 37 | ulong cpiv; |
| 38 | at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; |
| 39 | |
| 40 | cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); |
| 41 | |
| 42 | /* |
| 43 | * Disable PITC |
| 44 | * Add 0x1000 to current counter to stop it faster |
| 45 | * without waiting for wrapping back to 0 |
| 46 | */ |
| 47 | writel(cpiv + 0x1000, &pit->mr); |
Eugen Hristev | be6a85f | 2020-08-20 16:11:52 +0300 | [diff] [blame] | 48 | #endif |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 52 | int print_cpuinfo(void) |
| 53 | { |
| 54 | char buf[32]; |
| 55 | |
| 56 | printf("CPU: %s\n", get_cpu_name()); |
| 57 | printf("Crystal frequency: %8s MHz\n", |
| 58 | strmhz(buf, get_main_clk_rate())); |
| 59 | printf("CPU clock : %8s MHz\n", |
| 60 | strmhz(buf, get_cpu_clk_rate())); |
| 61 | printf("Master clock : %8s MHz\n", |
| 62 | strmhz(buf, get_mck_clk_rate())); |
| 63 | |
| 64 | return 0; |
| 65 | } |
| 66 | #endif |
| 67 | |
| 68 | void enable_caches(void) |
| 69 | { |
Wu, Josh | 4a5c5c3 | 2014-05-19 19:51:28 +0800 | [diff] [blame] | 70 | icache_enable(); |
| 71 | dcache_enable(); |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 72 | } |
| 73 | |
Wenyou Yang | 0a248bc | 2015-09-08 14:38:26 +0800 | [diff] [blame] | 74 | #define ATMEL_CHIPID_CIDR_VERSION 0x1f |
| 75 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 76 | unsigned int get_chip_id(void) |
| 77 | { |
Wenyou Yang | 0a248bc | 2015-09-08 14:38:26 +0800 | [diff] [blame] | 78 | return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION; |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 79 | } |
| 80 | |
| 81 | unsigned int get_extension_chip_id(void) |
| 82 | { |
Wenyou Yang | 0a248bc | 2015-09-08 14:38:26 +0800 | [diff] [blame] | 83 | return readl(ATMEL_CHIPID_EXID); |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 84 | } |