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git01.mediatek.com / filogic / uboot / 6a51f189f1572ebd7bf1cf0c6b320a532be8eab1 / . / drivers / misc / gdsys_ioep.h
blob: f195388edaf84a937df6e748345f671ec9a00010 [file] [log] [blame]
Mario Six0cafb652018-07-31 14:24:15 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2018
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
5 */
6
7#ifndef __GDSYS_IOEP_H_
8#define __GDSYS_IOEP_H_
9
10/**
11 * struct io_generic_packet - header structure for GDSYS IOEP packets
12 * @target_address: Target protocol address of the packet.
13 * @source_address: Source protocol address of the packet.
14 * @packet_type: Packet type.
15 * @bc: Block counter (filled in by FPGA).
16 * @packet_length: Length of the packet's payload bytes.
17 */
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]18#include <linux/bitops.h>
Mario Six0cafb652018-07-31 14:24:15 +0200[diff] [blame]19struct io_generic_packet {
20 u16 target_address;
21 u16 source_address;
22 u8 packet_type;
23 u8 bc;
24 u16 packet_length;
25} __attribute__((__packed__));
26
27/**
28 * struct gdsys_ioep_regs - Registers of a IOEP device
29 * @transmit_data: Register that receives data to be sent
30 * @tx_control: TX control register
31 * @receive_data: Register filled with the received data
32 * @rx_tx_status: RX/TX status register
33 * @device_address: Register for setting/reading the device's address
34 * @target_address: Register for setting/reading the remote endpoint's address
35 * @int_enable: Interrupt/Interrupt enable register
36 */
37struct gdsys_ioep_regs {
38 u16 transmit_data;
39 u16 tx_control;
40 u16 receive_data;
41 u16 rx_tx_status;
42 u16 device_address;
43 u16 target_address;
44 u16 int_enable;
45};
46
47/**
48 * gdsys_ioep_set() - Convenience macro to write registers of a IOEP device
49 * @map: Register map to write the value in
50 * @member: Name of the member in the gdsys_ioep_regs structure to write
51 * @val: Value to write to the register
52 */
53#define gdsys_ioep_set(map, member, val) \
54 regmap_set(map, struct gdsys_ioep_regs, member, val)
55
56/**
57 * gdsys_ioep_get() - Convenience macro to read registers of a IOEP device
58 * @map: Register map to read the value from
59 * @member: Name of the member in the gdsys_ioep_regs structure to read
60 * @valp: Pointer to buffer to read the register value into
61 */
62#define gdsys_ioep_get(map, member, valp) \
63 regmap_get(map, struct gdsys_ioep_regs, member, valp)
64
65/**
66 * enum rx_tx_status_values - Enum to describe the fields of the rx_tx_status
67 * register
68 * @STATE_TX_PACKET_BUILDING: The device is currently building a packet
69 * (and accepting data for it)
70 * @STATE_TX_TRANSMITTING: A packet is currenly being transmitted
71 * @STATE_TX_BUFFER_FULL: The TX buffer is full
72 * @STATE_TX_ERR: A TX error occurred
73 * @STATE_RECEIVE_TIMEOUT: A receive timeout occurred
74 * @STATE_PROC_RX_STORE_TIMEOUT: A RX store timeout for a processor packet
75 * occurred
76 * @STATE_PROC_RX_RECEIVE_TIMEOUT: A RX receive timeout for a processor packet
77 * occurred
78 * @STATE_RX_DIST_ERR: A error occurred in the distribution block
79 * @STATE_RX_LENGTH_ERR: A length invalid error occurred
80 * @STATE_RX_FRAME_CTR_ERR: A frame count error occurred (two
81 * non-increasing frame count numbers
82 * encountered)
83 * @STATE_RX_FCS_ERR: A CRC error occurred
84 * @STATE_RX_PACKET_DROPPED: A RX packet has been dropped
85 * @STATE_RX_DATA_LAST: The data to be read is the final data of the
86 * current packet
87 * @STATE_RX_DATA_FIRST: The data to be read is the first data of the
88 * current packet
89 * @STATE_RX_DATA_AVAILABLE: RX data is available to be read
90 */
91enum rx_tx_status_values {
92 STATE_TX_PACKET_BUILDING = BIT(0),
93 STATE_TX_TRANSMITTING = BIT(1),
94 STATE_TX_BUFFER_FULL = BIT(2),
95 STATE_TX_ERR = BIT(3),
96 STATE_RECEIVE_TIMEOUT = BIT(4),
97 STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
98 STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
99 STATE_RX_DIST_ERR = BIT(7),
100 STATE_RX_LENGTH_ERR = BIT(8),
101 STATE_RX_FRAME_CTR_ERR = BIT(9),
102 STATE_RX_FCS_ERR = BIT(10),
103 STATE_RX_PACKET_DROPPED = BIT(11),
104 STATE_RX_DATA_LAST = BIT(12),
105 STATE_RX_DATA_FIRST = BIT(13),
106 STATE_RX_DATA_AVAILABLE = BIT(15),
107};
108
109/**
110 * enum tx_control_values - Enum to describe the fields of the tx_control
111 * register
112 * @CTRL_PROC_RECEIVE_ENABLE: Enable packet reception for the processor
113 * @CTRL_FLUSH_TRANSMIT_BUFFER: Flush the transmit buffer (and send packet data)
114 */
115enum tx_control_values {
116 CTRL_PROC_RECEIVE_ENABLE = BIT(12),
117 CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
118};
119
120/**
121 * enum int_enable_values - Enum to describe the fields of the int_enable
122 * register
123 * @IRQ_CPU_TRANSMITBUFFER_FREE_STATUS: The transmit buffer is free (packet
124 * data can be transmitted to the
125 * device)
126 * @IRQ_CPU_PACKET_TRANSMITTED_EVENT: A packet has been transmitted
127 * @IRQ_NEW_CPU_PACKET_RECEIVED_EVENT: A new packet has been received
128 * @IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS: RX packet data are available to be
129 * read
130 */
131enum int_enable_values {
132 IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
133 IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
134 IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
135 IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
136};
137
138#endif /* __GDSYS_IOEP_H_ */