| Jean-Christophe PLAGNIOL-VILLARD | 06a819c | 2009-06-13 20:50:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-arm/macro.h |
| 3 | * |
| 4 | * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
| 5 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| Jean-Christophe PLAGNIOL-VILLARD | 06a819c | 2009-06-13 20:50:02 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_ARM_MACRO_H__ |
| 10 | #define __ASM_ARM_MACRO_H__ |
| 11 | #ifdef __ASSEMBLY__ |
| 12 | |
| 13 | /* |
| 14 | * These macros provide a convenient way to write 8, 16 and 32 bit data |
| 15 | * to any address. |
| 16 | * Registers r4 and r5 are used, any data in these registers are |
| 17 | * overwritten by the macros. |
| 18 | * The macros are valid for any ARM architecture, they do not implement |
| 19 | * any memory barriers so caution is recommended when using these when the |
| 20 | * caches are enabled or on a multi-core system. |
| 21 | */ |
| 22 | |
| 23 | .macro write32, addr, data |
| 24 | ldr r4, =\addr |
| 25 | ldr r5, =\data |
| 26 | str r5, [r4] |
| 27 | .endm |
| 28 | |
| 29 | .macro write16, addr, data |
| 30 | ldr r4, =\addr |
| 31 | ldrh r5, =\data |
| 32 | strh r5, [r4] |
| 33 | .endm |
| 34 | |
| 35 | .macro write8, addr, data |
| 36 | ldr r4, =\addr |
| 37 | ldrb r5, =\data |
| 38 | strb r5, [r4] |
| 39 | .endm |
| 40 | |
| 41 | /* |
| 42 | * This macro generates a loop that can be used for delays in the code. |
| 43 | * Register r4 is used, any data in this register is overwritten by the |
| 44 | * macro. |
| 45 | * The macro is valid for any ARM architeture. The actual time spent in the |
| 46 | * loop will vary from CPU to CPU though. |
| 47 | */ |
| 48 | |
| 49 | .macro wait_timer, time |
| 50 | ldr r4, =\time |
| 51 | 1: |
| 52 | nop |
| 53 | subs r4, r4, #1 |
| 54 | bcs 1b |
| 55 | .endm |
| 56 | |
| David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 57 | #ifdef CONFIG_ARM64 |
| 58 | /* |
| 59 | * Register aliases. |
| 60 | */ |
| 61 | lr .req x30 |
| 62 | |
| 63 | /* |
| 64 | * Branch according to exception level |
| 65 | */ |
| 66 | .macro switch_el, xreg, el3_label, el2_label, el1_label |
| 67 | mrs \xreg, CurrentEL |
| 68 | cmp \xreg, 0xc |
| 69 | b.eq \el3_label |
| 70 | cmp \xreg, 0x8 |
| 71 | b.eq \el2_label |
| 72 | cmp \xreg, 0x4 |
| 73 | b.eq \el1_label |
| 74 | .endm |
| 75 | |
| 76 | /* |
| 77 | * Branch if current processor is a slave, |
| 78 | * choose processor with all zero affinity value as the master. |
| 79 | */ |
| 80 | .macro branch_if_slave, xreg, slave_label |
| 81 | mrs \xreg, mpidr_el1 |
| 82 | tst \xreg, #0xff /* Test Affinity 0 */ |
| 83 | b.ne \slave_label |
| 84 | lsr \xreg, \xreg, #8 |
| 85 | tst \xreg, #0xff /* Test Affinity 1 */ |
| 86 | b.ne \slave_label |
| 87 | lsr \xreg, \xreg, #8 |
| 88 | tst \xreg, #0xff /* Test Affinity 2 */ |
| 89 | b.ne \slave_label |
| 90 | lsr \xreg, \xreg, #16 |
| 91 | tst \xreg, #0xff /* Test Affinity 3 */ |
| 92 | b.ne \slave_label |
| 93 | .endm |
| 94 | |
| 95 | /* |
| 96 | * Branch if current processor is a master, |
| 97 | * choose processor with all zero affinity value as the master. |
| 98 | */ |
| 99 | .macro branch_if_master, xreg1, xreg2, master_label |
| 100 | mrs \xreg1, mpidr_el1 |
| 101 | lsr \xreg2, \xreg1, #32 |
| 102 | lsl \xreg1, \xreg1, #40 |
| 103 | lsr \xreg1, \xreg1, #40 |
| 104 | orr \xreg1, \xreg1, \xreg2 |
| 105 | cbz \xreg1, \master_label |
| 106 | .endm |
| 107 | |
| 108 | #endif /* CONFIG_ARM64 */ |
| 109 | |
| Jean-Christophe PLAGNIOL-VILLARD | 06a819c | 2009-06-13 20:50:02 +0200 | [diff] [blame] | 110 | #endif /* __ASSEMBLY__ */ |
| 111 | #endif /* __ASM_ARM_MACRO_H__ */ |