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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Fabio Estevam6cfa7122016-02-29 09:33:22 -03002/*
3 * Copyright (C) 2016 NXP Semiconductors
4 * Author: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam6cfa7122016-02-29 09:33:22 -03005 */
6
Simon Glassa7b51302019-11-14 12:57:46 -07007#include <init.h>
Fabio Estevam6cfa7122016-02-29 09:33:22 -03008#include <asm/arch/clock.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/mx7-pins.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/gpio.h>
Bryan O'Donoghue1b60ee62018-04-24 18:46:33 +010013#include <asm/mach-imx/hab.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020014#include <asm/mach-imx/iomux-v3.h>
Fabio Estevam6cfa7122016-02-29 09:33:22 -030015#include <asm/io.h>
16#include <common.h>
Simon Glass07dc93c2019-08-01 09:46:47 -060017#include <env.h>
Fabio Estevam6cfa7122016-02-29 09:33:22 -030018#include <asm/arch/crm_regs.h>
Kevin Hilman46fdd842016-12-16 13:08:10 -080019#include <netdev.h>
Vanessa Maegima4abedc82016-08-19 10:21:36 -030020#include <power/pmic.h>
21#include <power/pfuze3000_pmic.h>
22#include "../freescale/common/pfuze.h"
Bryan O'Donoghue1936c412018-03-26 15:27:34 +010023#include <asm/setup.h>
24#include <asm/bootm.h>
Fabio Estevam6cfa7122016-02-29 09:33:22 -030025
26DECLARE_GLOBAL_DATA_PTR;
27
28#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
29 PAD_CTL_HYS)
Fabio Estevam6cfa7122016-02-29 09:33:22 -030030
31int dram_init(void)
32{
33 gd->ram_size = PHYS_SDRAM_SIZE;
34
Bryan O'Donoghue2adfdff2018-04-24 18:46:35 +010035 /* Subtract the defined OPTEE runtime firmware length */
36#ifdef CONFIG_OPTEE_TZDRAM_SIZE
37 gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
38#endif
39
Fabio Estevam6cfa7122016-02-29 09:33:22 -030040 return 0;
41}
42
Marco Franchi3d73f522016-06-10 14:45:28 -030043static iomux_v3_cfg_t const wdog_pads[] = {
44 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
45};
46
Fabio Estevam6cfa7122016-02-29 09:33:22 -030047static iomux_v3_cfg_t const uart1_pads[] = {
48 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
49 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
50};
51
Fabio Estevam6cfa7122016-02-29 09:33:22 -030052static void setup_iomux_uart(void)
53{
54 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
55};
56
Fabio Estevam6cfa7122016-02-29 09:33:22 -030057int board_early_init_f(void)
58{
59 setup_iomux_uart();
60
61 return 0;
62}
63
Bryan O'Donoghue6f1eee62019-01-18 17:40:14 +000064#ifdef CONFIG_DM_PMIC
Vanessa Maegima4abedc82016-08-19 10:21:36 -030065int power_init_board(void)
66{
Bryan O'Donoghue6f1eee62019-01-18 17:40:14 +000067 struct udevice *dev;
68 int ret, dev_id, rev_id;
Vanessa Maegima4abedc82016-08-19 10:21:36 -030069
Joris Offougae19e7cc2020-01-29 22:05:58 +010070 ret = pmic_get("pfuze3000@8", &dev);
Bryan O'Donoghue6f1eee62019-01-18 17:40:14 +000071 if (ret == -ENODEV)
72 return 0;
73 if (ret != 0)
Vanessa Maegima4abedc82016-08-19 10:21:36 -030074 return ret;
75
Bryan O'Donoghue6f1eee62019-01-18 17:40:14 +000076 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
77 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
78 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
Vanessa Maegima4abedc82016-08-19 10:21:36 -030079
80 /* disable Low Power Mode during standby mode */
Fabio Estevam7ac7b962019-02-14 11:37:51 -020081 pmic_reg_write(dev, PFUZE3000_LDOGCTL, 1);
Vanessa Maegima4abedc82016-08-19 10:21:36 -030082
83 return 0;
84}
85#endif
86
Kevin Hilman46fdd842016-12-16 13:08:10 -080087int board_eth_init(bd_t *bis)
88{
89 int ret = 0;
90
91#ifdef CONFIG_USB_ETHER
92 ret = usb_eth_initialize(bis);
93 if (ret < 0)
94 printf("Error %d registering USB ether.\n", ret);
95#endif
96
97 return ret;
98}
99
Fabio Estevam6cfa7122016-02-29 09:33:22 -0300100int board_init(void)
101{
102 /* address of boot parameters */
103 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
104
105 return 0;
106}
107
108int checkboard(void)
109{
Fabio Estevamf8f21942016-08-25 21:07:20 -0300110 char *mode;
111
112 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
113 mode = "secure";
114 else
115 mode = "non-secure";
116
Bryan O'Donoghue446dddd2018-04-24 18:46:36 +0100117#ifdef CONFIG_OPTEE_TZDRAM_SIZE
118 unsigned long optee_start, optee_end;
119
120 optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
121 optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
122
123 printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
124 mode, optee_start, optee_end);
125#else
Fabio Estevamf8f21942016-08-25 21:07:20 -0300126 printf("Board: WARP7 in %s mode\n", mode);
Bryan O'Donoghue446dddd2018-04-24 18:46:36 +0100127#endif
Fabio Estevam6cfa7122016-02-29 09:33:22 -0300128
129 return 0;
130}
131
Marco Franchi3d73f522016-06-10 14:45:28 -0300132int board_late_init(void)
133{
134 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
Bryan O'Donoghue1936c412018-03-26 15:27:34 +0100135#ifdef CONFIG_SERIAL_TAG
136 struct tag_serialnr serialnr;
137 char serial_string[0x20];
138#endif
Marco Franchi3d73f522016-06-10 14:45:28 -0300139
140 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
141
142 set_wdog_reset(wdog);
143
144 /*
145 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
146 * since we use PMIC_PWRON to reset the board.
147 */
148 clrsetbits_le16(&wdog->wcr, 0, 0x10);
149
Stefano Babicf8b509b2019-09-20 08:47:53 +0200150#ifdef CONFIG_IMX_HAB
Bryan O'Donoghue1b60ee62018-04-24 18:46:33 +0100151 /* Determine HAB state */
152 env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
153#else
154 env_set_ulong(HAB_ENABLED_ENVNAME, 0);
155#endif
156
Bryan O'Donoghue1936c412018-03-26 15:27:34 +0100157#ifdef CONFIG_SERIAL_TAG
158 /* Set serial# standard environment variable based on OTP settings */
159 get_board_serial(&serialnr);
160 snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
161 serialnr.low, serialnr.high);
162 env_set("serial#", serial_string);
163#endif
164
Marco Franchi3d73f522016-06-10 14:45:28 -0300165 return 0;
166}