blob: b6435f34f22adeec22909a730b3a72b7d6121b02 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05002/*
3 * pci.c -- WindRiver SBC8349 PCI board support.
4 * Copyright (c) 2006 Wind River Systems, Inc.
Kim Phillips57a2af32009-07-18 18:42:13 -05005 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05006 *
7 * Based on MPC8349 PCI support but w/o PIB related code.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05008 */
9
Simon Glass18afe102019-11-14 12:57:47 -070010#include <init.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050011#include <asm/mmu.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050012#include <asm/io.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050013#include <common.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050014#include <mpc83xx.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050015#include <pci.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050016#include <i2c.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050017#include <asm/fsl_i2c.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050018
Kim Phillips57a2af32009-07-18 18:42:13 -050019static struct pci_region pci1_regions[] = {
20 {
21 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
22 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
23 size: CONFIG_SYS_PCI1_MEM_SIZE,
24 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050025 },
Kim Phillips57a2af32009-07-18 18:42:13 -050026 {
27 bus_start: CONFIG_SYS_PCI1_IO_BASE,
28 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
29 size: CONFIG_SYS_PCI1_IO_SIZE,
30 flags: PCI_REGION_IO
31 },
32 {
33 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
34 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
35 size: CONFIG_SYS_PCI1_MMIO_SIZE,
36 flags: PCI_REGION_MEM
37 },
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050038};
39
Kim Phillips57a2af32009-07-18 18:42:13 -050040/*
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050041 * pci_init_board()
42 *
43 * NOTICE: PCI2 is not supported. There is only one
44 * physical PCI slot on the board.
45 *
46 */
47void
48pci_init_board(void)
49{
Kim Phillips57a2af32009-07-18 18:42:13 -050050 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
51 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
52 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
53 struct pci_region *reg[] = { pci1_regions };
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050054
Kim Phillips57a2af32009-07-18 18:42:13 -050055 /* Enable all 8 PCI_CLK_OUTPUTS */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050056 clk->occr = 0xff000000;
57 udelay(2000);
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050058
Kim Phillips57a2af32009-07-18 18:42:13 -050059 /* Configure PCI Local Access Windows */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050061 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
62
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050064 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
65
Kim Phillips57a2af32009-07-18 18:42:13 -050066 udelay(2000);
Kim Phillipsfd47a742007-12-20 14:09:22 -060067
Peter Tysere2283322010-09-14 19:13:50 -050068 mpc83xx_pci_init(1, reg);
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050069}