Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Google, Inc |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 6 | #include <common.h> |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 7 | #include <dm.h> |
| 8 | #include <asm/io.h> |
Bin Meng | 325eed9 | 2018-08-03 01:14:42 -0700 | [diff] [blame] | 9 | #include <asm/test.h> |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 10 | #include <dm/test.h> |
Simon Glass | 75c4d41 | 2020-07-19 10:15:37 -0600 | [diff] [blame] | 11 | #include <test/test.h> |
Joe Hershberger | 3a77be5 | 2015-05-20 14:27:27 -0500 | [diff] [blame] | 12 | #include <test/ut.h> |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 13 | |
| 14 | /* Test that sandbox PCI works correctly */ |
Joe Hershberger | 3a77be5 | 2015-05-20 14:27:27 -0500 | [diff] [blame] | 15 | static int dm_test_pci_base(struct unit_test_state *uts) |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 16 | { |
| 17 | struct udevice *bus; |
| 18 | |
| 19 | ut_assertok(uclass_get_device(UCLASS_PCI, 0, &bus)); |
| 20 | |
| 21 | return 0; |
| 22 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 23 | DM_TEST(dm_test_pci_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 24 | |
Bin Meng | cbf071b | 2018-08-03 01:14:39 -0700 | [diff] [blame] | 25 | /* Test that sandbox PCI bus numbering and device works correctly */ |
| 26 | static int dm_test_pci_busdev(struct unit_test_state *uts) |
Simon Glass | a814941 | 2015-05-10 21:08:06 -0600 | [diff] [blame] | 27 | { |
| 28 | struct udevice *bus; |
Bin Meng | 325eed9 | 2018-08-03 01:14:42 -0700 | [diff] [blame] | 29 | struct udevice *swap; |
| 30 | u16 vendor, device; |
Simon Glass | a814941 | 2015-05-10 21:08:06 -0600 | [diff] [blame] | 31 | |
Bin Meng | 408e590 | 2018-08-03 01:14:41 -0700 | [diff] [blame] | 32 | /* Test bus#0 and its devices */ |
Simon Glass | a814941 | 2015-05-10 21:08:06 -0600 | [diff] [blame] | 33 | ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus)); |
| 34 | |
Bin Meng | cbf071b | 2018-08-03 01:14:39 -0700 | [diff] [blame] | 35 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap)); |
Bin Meng | 325eed9 | 2018-08-03 01:14:42 -0700 | [diff] [blame] | 36 | vendor = 0; |
| 37 | ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor)); |
| 38 | ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor); |
Bin Meng | cbf071b | 2018-08-03 01:14:39 -0700 | [diff] [blame] | 39 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap)); |
Bin Meng | 325eed9 | 2018-08-03 01:14:42 -0700 | [diff] [blame] | 40 | device = 0; |
| 41 | ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device)); |
Simon Glass | 21c8f1a | 2019-09-25 08:56:01 -0600 | [diff] [blame] | 42 | ut_asserteq(SANDBOX_PCI_SWAP_CASE_EMUL_ID, device); |
Bin Meng | cbf071b | 2018-08-03 01:14:39 -0700 | [diff] [blame] | 43 | |
Bin Meng | 408e590 | 2018-08-03 01:14:41 -0700 | [diff] [blame] | 44 | /* Test bus#1 and its devices */ |
| 45 | ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus)); |
| 46 | |
Bin Meng | 408e590 | 2018-08-03 01:14:41 -0700 | [diff] [blame] | 47 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap)); |
Bin Meng | 325eed9 | 2018-08-03 01:14:42 -0700 | [diff] [blame] | 48 | vendor = 0; |
| 49 | ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor)); |
| 50 | ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor); |
Bin Meng | 408e590 | 2018-08-03 01:14:41 -0700 | [diff] [blame] | 51 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap)); |
Bin Meng | 325eed9 | 2018-08-03 01:14:42 -0700 | [diff] [blame] | 52 | device = 0; |
| 53 | ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device)); |
Simon Glass | 21c8f1a | 2019-09-25 08:56:01 -0600 | [diff] [blame] | 54 | ut_asserteq(SANDBOX_PCI_SWAP_CASE_EMUL_ID, device); |
Bin Meng | 408e590 | 2018-08-03 01:14:41 -0700 | [diff] [blame] | 55 | |
Simon Glass | a814941 | 2015-05-10 21:08:06 -0600 | [diff] [blame] | 56 | return 0; |
| 57 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 58 | DM_TEST(dm_test_pci_busdev, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Simon Glass | a814941 | 2015-05-10 21:08:06 -0600 | [diff] [blame] | 59 | |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 60 | /* Test that we can use the swapcase device correctly */ |
Joe Hershberger | 3a77be5 | 2015-05-20 14:27:27 -0500 | [diff] [blame] | 61 | static int dm_test_pci_swapcase(struct unit_test_state *uts) |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 62 | { |
Bin Meng | 1445042 | 2018-08-03 01:14:38 -0700 | [diff] [blame] | 63 | struct udevice *swap; |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 64 | ulong io_addr, mem_addr; |
| 65 | char *ptr; |
| 66 | |
Bin Meng | cbf071b | 2018-08-03 01:14:39 -0700 | [diff] [blame] | 67 | /* Check that asking for the device 0 automatically fires up PCI */ |
| 68 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap)); |
| 69 | |
| 70 | /* First test I/O */ |
| 71 | io_addr = dm_pci_read_bar32(swap, 0); |
| 72 | outb(2, io_addr); |
| 73 | ut_asserteq(2, inb(io_addr)); |
| 74 | |
| 75 | /* |
| 76 | * Now test memory mapping - note we must unmap and remap to cause |
| 77 | * the swapcase emulation to see our data and response. |
| 78 | */ |
| 79 | mem_addr = dm_pci_read_bar32(swap, 1); |
| 80 | ptr = map_sysmem(mem_addr, 20); |
| 81 | strcpy(ptr, "This is a TesT"); |
| 82 | unmap_sysmem(ptr); |
| 83 | |
| 84 | ptr = map_sysmem(mem_addr, 20); |
| 85 | ut_asserteq_str("tHIS IS A tESt", ptr); |
| 86 | unmap_sysmem(ptr); |
| 87 | |
| 88 | /* Check that asking for the device 1 automatically fires up PCI */ |
Simon Glass | 0120d46 | 2015-11-29 13:18:02 -0700 | [diff] [blame] | 89 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap)); |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 90 | |
| 91 | /* First test I/O */ |
Simon Glass | 0120d46 | 2015-11-29 13:18:02 -0700 | [diff] [blame] | 92 | io_addr = dm_pci_read_bar32(swap, 0); |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 93 | outb(2, io_addr); |
| 94 | ut_asserteq(2, inb(io_addr)); |
| 95 | |
| 96 | /* |
| 97 | * Now test memory mapping - note we must unmap and remap to cause |
| 98 | * the swapcase emulation to see our data and response. |
| 99 | */ |
Simon Glass | 0120d46 | 2015-11-29 13:18:02 -0700 | [diff] [blame] | 100 | mem_addr = dm_pci_read_bar32(swap, 1); |
Simon Glass | 3a6eae6 | 2015-03-05 12:25:34 -0700 | [diff] [blame] | 101 | ptr = map_sysmem(mem_addr, 20); |
| 102 | strcpy(ptr, "This is a TesT"); |
| 103 | unmap_sysmem(ptr); |
| 104 | |
| 105 | ptr = map_sysmem(mem_addr, 20); |
| 106 | ut_asserteq_str("tHIS IS A tESt", ptr); |
| 107 | unmap_sysmem(ptr); |
| 108 | |
| 109 | return 0; |
| 110 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 111 | DM_TEST(dm_test_pci_swapcase, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Bin Meng | 4e08073 | 2018-08-03 01:14:48 -0700 | [diff] [blame] | 112 | |
| 113 | /* Test that we can dynamically bind the device driver correctly */ |
| 114 | static int dm_test_pci_drvdata(struct unit_test_state *uts) |
| 115 | { |
| 116 | struct udevice *bus, *swap; |
| 117 | |
| 118 | /* Check that asking for the device automatically fires up PCI */ |
| 119 | ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus)); |
| 120 | |
| 121 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap)); |
| 122 | ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data); |
Simon Glass | f1d50f7 | 2020-12-19 10:40:13 -0700 | [diff] [blame] | 123 | ut_assertok(dev_has_ofnode(swap)); |
Bin Meng | 4e08073 | 2018-08-03 01:14:48 -0700 | [diff] [blame] | 124 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap)); |
| 125 | ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data); |
Simon Glass | f1d50f7 | 2020-12-19 10:40:13 -0700 | [diff] [blame] | 126 | ut_assertok(dev_has_ofnode(swap)); |
Marek Vasut | c17d162 | 2018-10-10 21:27:09 +0200 | [diff] [blame] | 127 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x10, 0), &swap)); |
| 128 | ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data); |
Simon Glass | f1d50f7 | 2020-12-19 10:40:13 -0700 | [diff] [blame] | 129 | ut_assertok(!dev_has_ofnode(swap)); |
Bin Meng | 4e08073 | 2018-08-03 01:14:48 -0700 | [diff] [blame] | 130 | |
| 131 | return 0; |
| 132 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 133 | DM_TEST(dm_test_pci_drvdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Bin Meng | 510dddb | 2018-08-03 01:14:50 -0700 | [diff] [blame] | 134 | |
| 135 | /* Test that devices on PCI bus#2 can be accessed correctly */ |
| 136 | static int dm_test_pci_mixed(struct unit_test_state *uts) |
| 137 | { |
| 138 | /* PCI bus#2 has both statically and dynamic declared devices */ |
| 139 | struct udevice *bus, *swap; |
| 140 | u16 vendor, device; |
| 141 | ulong io_addr, mem_addr; |
| 142 | char *ptr; |
| 143 | |
| 144 | ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 2, &bus)); |
| 145 | |
| 146 | /* Test the dynamic device */ |
| 147 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(2, 0x08, 0), &swap)); |
| 148 | vendor = 0; |
| 149 | ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor)); |
| 150 | ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor); |
| 151 | |
| 152 | /* First test I/O */ |
| 153 | io_addr = dm_pci_read_bar32(swap, 0); |
| 154 | outb(2, io_addr); |
| 155 | ut_asserteq(2, inb(io_addr)); |
| 156 | |
| 157 | /* |
| 158 | * Now test memory mapping - note we must unmap and remap to cause |
| 159 | * the swapcase emulation to see our data and response. |
| 160 | */ |
| 161 | mem_addr = dm_pci_read_bar32(swap, 1); |
| 162 | ptr = map_sysmem(mem_addr, 30); |
| 163 | strcpy(ptr, "This is a TesT oN dYNAMIc"); |
| 164 | unmap_sysmem(ptr); |
| 165 | |
| 166 | ptr = map_sysmem(mem_addr, 30); |
| 167 | ut_asserteq_str("tHIS IS A tESt On DynamiC", ptr); |
| 168 | unmap_sysmem(ptr); |
| 169 | |
| 170 | /* Test the static device */ |
| 171 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(2, 0x1f, 0), &swap)); |
| 172 | device = 0; |
| 173 | ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device)); |
Simon Glass | 21c8f1a | 2019-09-25 08:56:01 -0600 | [diff] [blame] | 174 | ut_asserteq(SANDBOX_PCI_SWAP_CASE_EMUL_ID, device); |
Bin Meng | 510dddb | 2018-08-03 01:14:50 -0700 | [diff] [blame] | 175 | |
| 176 | /* First test I/O */ |
| 177 | io_addr = dm_pci_read_bar32(swap, 0); |
| 178 | outb(2, io_addr); |
| 179 | ut_asserteq(2, inb(io_addr)); |
| 180 | |
| 181 | /* |
| 182 | * Now test memory mapping - note we must unmap and remap to cause |
| 183 | * the swapcase emulation to see our data and response. |
| 184 | */ |
| 185 | mem_addr = dm_pci_read_bar32(swap, 1); |
| 186 | ptr = map_sysmem(mem_addr, 30); |
| 187 | strcpy(ptr, "This is a TesT oN sTATIc"); |
| 188 | unmap_sysmem(ptr); |
| 189 | |
| 190 | ptr = map_sysmem(mem_addr, 30); |
| 191 | ut_asserteq_str("tHIS IS A tESt On StatiC", ptr); |
| 192 | unmap_sysmem(ptr); |
| 193 | |
| 194 | return 0; |
| 195 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 196 | DM_TEST(dm_test_pci_mixed, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Bin Meng | d74d312 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 197 | |
| 198 | /* Test looking up PCI capability and extended capability */ |
| 199 | static int dm_test_pci_cap(struct unit_test_state *uts) |
| 200 | { |
| 201 | struct udevice *bus, *swap; |
| 202 | int cap; |
| 203 | |
| 204 | ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus)); |
| 205 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap)); |
| 206 | |
| 207 | /* look up PCI_CAP_ID_EXP */ |
| 208 | cap = dm_pci_find_capability(swap, PCI_CAP_ID_EXP); |
| 209 | ut_asserteq(PCI_CAP_ID_EXP_OFFSET, cap); |
| 210 | |
| 211 | /* look up PCI_CAP_ID_PCIX */ |
| 212 | cap = dm_pci_find_capability(swap, PCI_CAP_ID_PCIX); |
| 213 | ut_asserteq(0, cap); |
| 214 | |
Bin Meng | b59b369 | 2018-10-15 02:21:22 -0700 | [diff] [blame] | 215 | /* look up PCI_CAP_ID_MSIX starting from PCI_CAP_ID_PM_OFFSET */ |
| 216 | cap = dm_pci_find_next_capability(swap, PCI_CAP_ID_PM_OFFSET, |
| 217 | PCI_CAP_ID_MSIX); |
| 218 | ut_asserteq(PCI_CAP_ID_MSIX_OFFSET, cap); |
| 219 | |
| 220 | /* look up PCI_CAP_ID_VNDR starting from PCI_CAP_ID_EXP_OFFSET */ |
| 221 | cap = dm_pci_find_next_capability(swap, PCI_CAP_ID_EXP_OFFSET, |
| 222 | PCI_CAP_ID_VNDR); |
| 223 | ut_asserteq(0, cap); |
| 224 | |
Bin Meng | d74d312 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 225 | ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus)); |
| 226 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap)); |
| 227 | |
| 228 | /* look up PCI_EXT_CAP_ID_DSN */ |
| 229 | cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_DSN); |
| 230 | ut_asserteq(PCI_EXT_CAP_ID_DSN_OFFSET, cap); |
| 231 | |
| 232 | /* look up PCI_EXT_CAP_ID_SRIOV */ |
| 233 | cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_SRIOV); |
| 234 | ut_asserteq(0, cap); |
| 235 | |
Bin Meng | b59b369 | 2018-10-15 02:21:22 -0700 | [diff] [blame] | 236 | /* look up PCI_EXT_CAP_ID_DSN starting from PCI_EXT_CAP_ID_ERR_OFFSET */ |
| 237 | cap = dm_pci_find_next_ext_capability(swap, PCI_EXT_CAP_ID_ERR_OFFSET, |
| 238 | PCI_EXT_CAP_ID_DSN); |
| 239 | ut_asserteq(PCI_EXT_CAP_ID_DSN_OFFSET, cap); |
| 240 | |
| 241 | /* look up PCI_EXT_CAP_ID_RCRB starting from PCI_EXT_CAP_ID_VC_OFFSET */ |
| 242 | cap = dm_pci_find_next_ext_capability(swap, PCI_EXT_CAP_ID_VC_OFFSET, |
| 243 | PCI_EXT_CAP_ID_RCRB); |
| 244 | ut_asserteq(0, cap); |
| 245 | |
Bin Meng | d74d312 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 246 | return 0; |
| 247 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 248 | DM_TEST(dm_test_pci_cap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 249 | |
| 250 | /* Test looking up BARs in EA capability structure */ |
| 251 | static int dm_test_pci_ea(struct unit_test_state *uts) |
| 252 | { |
| 253 | struct udevice *bus, *swap; |
| 254 | void *bar; |
| 255 | int cap; |
| 256 | |
| 257 | /* |
| 258 | * use emulated device mapping function, we're not using real physical |
| 259 | * addresses in this test |
| 260 | */ |
| 261 | sandbox_set_enable_pci_map(true); |
| 262 | |
| 263 | ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus)); |
| 264 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x01, 0), &swap)); |
| 265 | |
| 266 | /* look up PCI_CAP_ID_EA */ |
| 267 | cap = dm_pci_find_capability(swap, PCI_CAP_ID_EA); |
| 268 | ut_asserteq(PCI_CAP_ID_EA_OFFSET, cap); |
| 269 | |
| 270 | /* test swap case in BAR 1 */ |
Andrew Scull | 6520c82 | 2022-04-21 16:11:13 +0000 | [diff] [blame] | 271 | bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0); |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 272 | ut_assertnonnull(bar); |
| 273 | *(int *)bar = 2; /* swap upper/lower */ |
| 274 | |
Andrew Scull | 6520c82 | 2022-04-21 16:11:13 +0000 | [diff] [blame] | 275 | bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, 0); |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 276 | ut_assertnonnull(bar); |
| 277 | strcpy(bar, "ea TEST"); |
| 278 | unmap_sysmem(bar); |
Andrew Scull | 6520c82 | 2022-04-21 16:11:13 +0000 | [diff] [blame] | 279 | bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, 0); |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 280 | ut_assertnonnull(bar); |
| 281 | ut_asserteq_str("EA test", bar); |
| 282 | |
| 283 | /* test magic values in BARs2, 4; BAR 3 is n/a */ |
Andrew Scull | 6520c82 | 2022-04-21 16:11:13 +0000 | [diff] [blame] | 284 | bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE, 0); |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 285 | ut_assertnonnull(bar); |
| 286 | ut_asserteq(PCI_EA_BAR2_MAGIC, *(u32 *)bar); |
| 287 | |
Andrew Scull | 6520c82 | 2022-04-21 16:11:13 +0000 | [diff] [blame] | 288 | bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_3, 0, 0, PCI_REGION_TYPE, 0); |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 289 | ut_assertnull(bar); |
| 290 | |
Andrew Scull | 6520c82 | 2022-04-21 16:11:13 +0000 | [diff] [blame] | 291 | bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE, 0); |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 292 | ut_assertnonnull(bar); |
| 293 | ut_asserteq(PCI_EA_BAR4_MAGIC, *(u32 *)bar); |
| 294 | |
| 295 | return 0; |
| 296 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 297 | DM_TEST(dm_test_pci_ea, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 298 | |
| 299 | /* Test the dev_read_addr_pci() function */ |
| 300 | static int dm_test_pci_addr_flat(struct unit_test_state *uts) |
| 301 | { |
| 302 | struct udevice *swap1f, *swap1; |
| 303 | ulong io_addr, mem_addr; |
Simon Glass | 4289c26 | 2023-09-26 08:14:58 -0600 | [diff] [blame] | 304 | fdt_addr_t size; |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 305 | |
| 306 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap1f)); |
| 307 | io_addr = dm_pci_read_bar32(swap1f, 0); |
Simon Glass | 4289c26 | 2023-09-26 08:14:58 -0600 | [diff] [blame] | 308 | ut_asserteq(io_addr, dev_read_addr_pci(swap1f, &size)); |
| 309 | ut_asserteq(0, size); |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 310 | |
| 311 | /* |
| 312 | * This device has both I/O and MEM spaces but the MEM space appears |
| 313 | * first |
| 314 | */ |
| 315 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1, 0), &swap1)); |
| 316 | mem_addr = dm_pci_read_bar32(swap1, 1); |
Simon Glass | 4289c26 | 2023-09-26 08:14:58 -0600 | [diff] [blame] | 317 | ut_asserteq(mem_addr, dev_read_addr_pci(swap1, &size)); |
| 318 | ut_asserteq(0, size); |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 319 | |
| 320 | return 0; |
| 321 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 322 | DM_TEST(dm_test_pci_addr_flat, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | |
| 323 | UT_TESTF_FLAT_TREE); |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 324 | |
| 325 | /* |
| 326 | * Test the dev_read_addr_pci() function with livetree. That function is |
| 327 | * not currently fully implemented, in that it fails to return the BAR address. |
| 328 | * Once that is implemented this test can be removed and dm_test_pci_addr_flat() |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 329 | * can be used for both flattree and livetree by removing the UT_TESTF_FLAT_TREE |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 330 | * flag above. |
| 331 | */ |
| 332 | static int dm_test_pci_addr_live(struct unit_test_state *uts) |
| 333 | { |
| 334 | struct udevice *swap1f, *swap1; |
Simon Glass | 4289c26 | 2023-09-26 08:14:58 -0600 | [diff] [blame] | 335 | fdt_size_t size; |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 336 | |
| 337 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap1f)); |
Simon Glass | 4289c26 | 2023-09-26 08:14:58 -0600 | [diff] [blame] | 338 | ut_asserteq_64(FDT_ADDR_T_NONE, dev_read_addr_pci(swap1f, &size)); |
| 339 | ut_asserteq(0, size); |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 340 | |
| 341 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1, 0), &swap1)); |
Simon Glass | 4289c26 | 2023-09-26 08:14:58 -0600 | [diff] [blame] | 342 | ut_asserteq_64(FDT_ADDR_T_NONE, dev_read_addr_pci(swap1, &size)); |
| 343 | ut_asserteq(0, size); |
Simon Glass | 23b2759 | 2019-09-15 12:08:58 -0600 | [diff] [blame] | 344 | |
| 345 | return 0; |
| 346 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 347 | DM_TEST(dm_test_pci_addr_live, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | |
| 348 | UT_TESTF_LIVE_TREE); |
Simon Glass | 6ad24f6 | 2020-07-07 13:12:10 -0600 | [diff] [blame] | 349 | |
| 350 | /* Test device_is_on_pci_bus() */ |
| 351 | static int dm_test_pci_on_bus(struct unit_test_state *uts) |
| 352 | { |
| 353 | struct udevice *dev; |
| 354 | |
| 355 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &dev)); |
| 356 | ut_asserteq(true, device_is_on_pci_bus(dev)); |
| 357 | ut_asserteq(false, device_is_on_pci_bus(dev_get_parent(dev))); |
| 358 | ut_asserteq(true, device_is_on_pci_bus(dev)); |
| 359 | |
| 360 | return 0; |
| 361 | } |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 362 | DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Suneel Garapati | 3ac3aec | 2019-10-19 17:10:20 -0700 | [diff] [blame] | 363 | |
| 364 | /* |
| 365 | * Test support for multiple memory regions enabled via |
| 366 | * CONFIG_PCI_REGION_MULTI_ENTRY. When this feature is not enabled, |
| 367 | * only the last region of one type is stored. In this test-case, |
| 368 | * we have 2 memory regions, the first at 0x3000.0000 and the 2nd |
| 369 | * at 0x3100.0000. A correct test results now in BAR1 located at |
| 370 | * 0x3000.0000. |
| 371 | */ |
| 372 | static int dm_test_pci_region_multi(struct unit_test_state *uts) |
| 373 | { |
| 374 | struct udevice *dev; |
| 375 | ulong mem_addr; |
| 376 | |
| 377 | /* Test memory BAR1 on bus#1 */ |
| 378 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev)); |
| 379 | mem_addr = dm_pci_read_bar32(dev, 1); |
| 380 | ut_asserteq(mem_addr, 0x30000000); |
| 381 | |
| 382 | return 0; |
| 383 | } |
| 384 | DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 385 | |
| 386 | /* |
| 387 | * Test the translation of PCI bus addresses to physical addresses using the |
| 388 | * ranges from bus#1. |
| 389 | */ |
| 390 | static int dm_test_pci_bus_to_phys(struct unit_test_state *uts) |
| 391 | { |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 392 | unsigned long mask = PCI_REGION_TYPE; |
| 393 | unsigned long flags = PCI_REGION_MEM; |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 394 | struct udevice *dev; |
| 395 | phys_addr_t phys_addr; |
| 396 | |
| 397 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev)); |
| 398 | |
| 399 | /* Before any of the ranges. */ |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 400 | phys_addr = dm_pci_bus_to_phys(dev, 0x20000000, 0x400, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 401 | ut_asserteq(0, phys_addr); |
| 402 | |
| 403 | /* Identity range: whole, start, mid, end */ |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 404 | phys_addr = dm_pci_bus_to_phys(dev, 0x2ffff000, 0x2000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 405 | ut_asserteq(0, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 406 | phys_addr = dm_pci_bus_to_phys(dev, 0x30000000, 0x2000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 407 | ut_asserteq(0x30000000, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 408 | phys_addr = dm_pci_bus_to_phys(dev, 0x30000000, 0x1000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 409 | ut_asserteq(0x30000000, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 410 | phys_addr = dm_pci_bus_to_phys(dev, 0x30000abc, 0x12, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 411 | ut_asserteq(0x30000abc, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 412 | phys_addr = dm_pci_bus_to_phys(dev, 0x30000800, 0x1800, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 413 | ut_asserteq(0x30000800, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 414 | phys_addr = dm_pci_bus_to_phys(dev, 0x30008000, 0x1801, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 415 | ut_asserteq(0, phys_addr); |
| 416 | |
| 417 | /* Translated range: whole, start, mid, end */ |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 418 | phys_addr = dm_pci_bus_to_phys(dev, 0x30fff000, 0x2000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 419 | ut_asserteq(0, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 420 | phys_addr = dm_pci_bus_to_phys(dev, 0x31000000, 0x2000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 421 | ut_asserteq(0x3e000000, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 422 | phys_addr = dm_pci_bus_to_phys(dev, 0x31000000, 0x1000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 423 | ut_asserteq(0x3e000000, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 424 | phys_addr = dm_pci_bus_to_phys(dev, 0x31000abc, 0x12, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 425 | ut_asserteq(0x3e000abc, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 426 | phys_addr = dm_pci_bus_to_phys(dev, 0x31000800, 0x1800, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 427 | ut_asserteq(0x3e000800, phys_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 428 | phys_addr = dm_pci_bus_to_phys(dev, 0x31008000, 0x1801, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 429 | ut_asserteq(0, phys_addr); |
| 430 | |
| 431 | /* Beyond all of the ranges. */ |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 432 | phys_addr = dm_pci_bus_to_phys(dev, 0x32000000, 0x400, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 433 | ut_asserteq(0, phys_addr); |
| 434 | |
| 435 | return 0; |
| 436 | } |
| 437 | DM_TEST(dm_test_pci_bus_to_phys, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |
| 438 | |
| 439 | /* |
| 440 | * Test the translation of physical addresses to PCI bus addresses using the |
| 441 | * ranges from bus#1. |
| 442 | */ |
| 443 | static int dm_test_pci_phys_to_bus(struct unit_test_state *uts) |
| 444 | { |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 445 | unsigned long mask = PCI_REGION_TYPE; |
| 446 | unsigned long flags = PCI_REGION_MEM; |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 447 | struct udevice *dev; |
| 448 | pci_addr_t pci_addr; |
| 449 | |
| 450 | ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev)); |
| 451 | |
| 452 | /* Before any of the ranges. */ |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 453 | pci_addr = dm_pci_phys_to_bus(dev, 0x20000000, 0x400, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 454 | ut_asserteq(0, pci_addr); |
| 455 | |
| 456 | /* Identity range: partial overlap, whole, start, mid, end */ |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 457 | pci_addr = dm_pci_phys_to_bus(dev, 0x2ffff000, 0x2000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 458 | ut_asserteq(0, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 459 | pci_addr = dm_pci_phys_to_bus(dev, 0x30000000, 0x2000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 460 | ut_asserteq(0x30000000, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 461 | pci_addr = dm_pci_phys_to_bus(dev, 0x30000000, 0x1000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 462 | ut_asserteq(0x30000000, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 463 | pci_addr = dm_pci_phys_to_bus(dev, 0x30000abc, 0x12, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 464 | ut_asserteq(0x30000abc, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 465 | pci_addr = dm_pci_phys_to_bus(dev, 0x30000800, 0x1800, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 466 | ut_asserteq(0x30000800, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 467 | pci_addr = dm_pci_phys_to_bus(dev, 0x30008000, 0x1801, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 468 | ut_asserteq(0, pci_addr); |
| 469 | |
| 470 | /* Translated range: partial overlap, whole, start, mid, end */ |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 471 | pci_addr = dm_pci_phys_to_bus(dev, 0x3dfff000, 0x2000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 472 | ut_asserteq(0, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 473 | pci_addr = dm_pci_phys_to_bus(dev, 0x3e000000, 0x2000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 474 | ut_asserteq(0x31000000, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 475 | pci_addr = dm_pci_phys_to_bus(dev, 0x3e000000, 0x1000, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 476 | ut_asserteq(0x31000000, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 477 | pci_addr = dm_pci_phys_to_bus(dev, 0x3e000abc, 0x12, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 478 | ut_asserteq(0x31000abc, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 479 | pci_addr = dm_pci_phys_to_bus(dev, 0x3e000800, 0x1800, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 480 | ut_asserteq(0x31000800, pci_addr); |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 481 | pci_addr = dm_pci_phys_to_bus(dev, 0x3e008000, 0x1801, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 482 | ut_asserteq(0, pci_addr); |
| 483 | |
| 484 | /* Beyond all of the ranges. */ |
Andrew Scull | 994b60d | 2022-04-21 16:11:11 +0000 | [diff] [blame] | 485 | pci_addr = dm_pci_phys_to_bus(dev, 0x3f000000, 0x400, mask, flags); |
Andrew Scull | c7456a4 | 2022-04-21 16:11:09 +0000 | [diff] [blame] | 486 | ut_asserteq(0, pci_addr); |
| 487 | |
| 488 | return 0; |
| 489 | } |
| 490 | DM_TEST(dm_test_pci_phys_to_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |