Sumit Garg | 46ad40b | 2022-07-12 12:42:10 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Qualcomm QCS404 pinctrl |
| 4 | * |
| 5 | * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> |
| 6 | */ |
| 7 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 8 | #include <common.h> |
Caleb Connolly | 506eb53 | 2023-11-14 12:55:40 +0000 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | |
| 11 | #include "pinctrl-qcom.h" |
Sumit Garg | 46ad40b | 2022-07-12 12:42:10 +0530 | [diff] [blame] | 12 | |
Caleb Connolly | ab6a1ac | 2024-02-26 17:26:18 +0000 | [diff] [blame] | 13 | #define NORTH 0x00300000 |
| 14 | #define SOUTH 0x00000000 |
| 15 | #define EAST 0x06b00000 |
| 16 | |
Sumit Garg | 46ad40b | 2022-07-12 12:42:10 +0530 | [diff] [blame] | 17 | #define MAX_PIN_NAME_LEN 32 |
| 18 | static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); |
| 19 | static const char * const msm_pinctrl_pins[] = { |
Caleb Connolly | ab6a1ac | 2024-02-26 17:26:18 +0000 | [diff] [blame] | 20 | "sdc1_rclk", |
| 21 | "sdc1_clk", |
| 22 | "sdc1_cmd", |
| 23 | "sdc1_data", |
| 24 | "sdc2_clk", |
| 25 | "sdc2_cmd", |
| 26 | "sdc2_data", |
Sumit Garg | 46ad40b | 2022-07-12 12:42:10 +0530 | [diff] [blame] | 27 | }; |
| 28 | |
| 29 | static const struct pinctrl_function msm_pinctrl_functions[] = { |
Caleb Connolly | ab6a1ac | 2024-02-26 17:26:18 +0000 | [diff] [blame] | 30 | {"gpio", 0}, |
Sumit Garg | 09aea5d | 2023-02-01 19:28:51 +0530 | [diff] [blame] | 31 | {"rgmii_int", 1}, |
| 32 | {"rgmii_ck", 1}, |
| 33 | {"rgmii_tx", 1}, |
| 34 | {"rgmii_ctl", 1}, |
| 35 | {"rgmii_rx", 1}, |
| 36 | {"rgmii_mdio", 1}, |
| 37 | {"rgmii_mdc", 1}, |
Sumit Garg | 00e8469 | 2023-02-01 19:28:59 +0530 | [diff] [blame] | 38 | {"blsp_i2c0", 3}, |
| 39 | {"blsp_i2c1", 2}, |
| 40 | {"blsp_i2c_sda_a2", 3}, |
| 41 | {"blsp_i2c_scl_a2", 3}, |
| 42 | {"blsp_i2c3", 2}, |
| 43 | {"blsp_i2c4", 1}, |
Caleb Connolly | ab6a1ac | 2024-02-26 17:26:18 +0000 | [diff] [blame] | 44 | {"blsp_uart_tx_a2", 1}, |
| 45 | {"blsp_uart_rx_a2", 1}, |
| 46 | }; |
| 47 | |
| 48 | static const unsigned int qcs404_pin_offsets[] = { |
| 49 | [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, [4] = SOUTH, |
| 50 | [5] = SOUTH, [6] = SOUTH, [7] = SOUTH, [8] = SOUTH, [9] = SOUTH, |
| 51 | [10] = SOUTH, [11] = SOUTH, [12] = SOUTH, [13] = SOUTH, [14] = SOUTH, |
| 52 | [15] = SOUTH, [16] = SOUTH, [17] = NORTH, [18] = NORTH, [19] = NORTH, |
| 53 | [20] = NORTH, [21] = SOUTH, [22] = NORTH, [23] = NORTH, [24] = NORTH, |
| 54 | [25] = NORTH, [26] = EAST, [27] = EAST, [28] = EAST, [29] = EAST, |
| 55 | [30] = NORTH, [31] = NORTH, [32] = NORTH, [33] = NORTH, [34] = SOUTH, |
| 56 | [35] = SOUTH, [36] = NORTH, [37] = NORTH, [38] = NORTH, [39] = EAST, |
| 57 | [40] = EAST, [41] = EAST, [42] = EAST, [43] = EAST, [44] = EAST, |
| 58 | [45] = EAST, [46] = EAST, [47] = EAST, [48] = EAST, [49] = EAST, |
| 59 | [50] = EAST, [51] = EAST, [52] = EAST, [53] = EAST, [54] = EAST, |
| 60 | [55] = EAST, [56] = EAST, [57] = EAST, [58] = EAST, [59] = EAST, |
| 61 | [60] = NORTH, [61] = NORTH, [62] = NORTH, [63] = NORTH, [64] = NORTH, |
| 62 | [65] = NORTH, [66] = NORTH, [67] = NORTH, [68] = NORTH, [69] = NORTH, |
| 63 | [70] = NORTH, [71] = NORTH, [72] = NORTH, [73] = NORTH, [74] = NORTH, |
| 64 | [75] = NORTH, [76] = NORTH, [77] = NORTH, [78] = EAST, [79] = EAST, |
| 65 | [80] = EAST, [81] = EAST, [82] = NORTH, [83] = NORTH, [84] = NORTH, |
| 66 | [85] = NORTH, [86] = EAST, [87] = EAST, [88] = EAST, [89] = EAST, |
| 67 | [90] = EAST, [91] = EAST, [92] = EAST, [93] = EAST, [94] = EAST, |
| 68 | [95] = EAST, [96] = EAST, [97] = EAST, [98] = EAST, [99] = EAST, |
| 69 | [100] = EAST, [101] = EAST, [102] = EAST, [103] = EAST, [104] = EAST, |
| 70 | [105] = EAST, [106] = EAST, [107] = EAST, [108] = EAST, [109] = EAST, |
| 71 | [110] = EAST, [111] = EAST, [112] = EAST, [113] = EAST, [114] = EAST, |
| 72 | [115] = EAST, [116] = EAST, [117] = NORTH, [118] = NORTH, [119] = EAST, |
| 73 | /* |
| 74 | * There's 126 pins but the last ones are special and have non-standard registers |
| 75 | * so we leave them out here. The pinctrl and GPIO drivers both currently ignore |
| 76 | * these pins. |
| 77 | */ |
Sumit Garg | 46ad40b | 2022-07-12 12:42:10 +0530 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | static const char *qcs404_get_function_name(struct udevice *dev, |
| 81 | unsigned int selector) |
| 82 | { |
| 83 | return msm_pinctrl_functions[selector].name; |
| 84 | } |
| 85 | |
| 86 | static const char *qcs404_get_pin_name(struct udevice *dev, |
| 87 | unsigned int selector) |
| 88 | { |
| 89 | if (selector < 120) { |
Caleb Connolly | ab6a1ac | 2024-02-26 17:26:18 +0000 | [diff] [blame] | 90 | snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); |
Sumit Garg | 46ad40b | 2022-07-12 12:42:10 +0530 | [diff] [blame] | 91 | return pin_name; |
| 92 | } else { |
| 93 | return msm_pinctrl_pins[selector - 120]; |
| 94 | } |
| 95 | } |
| 96 | |
Volodymyr Babchuk | c4cc979 | 2024-03-11 21:33:46 +0000 | [diff] [blame] | 97 | static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin, |
| 98 | unsigned int selector) |
Sumit Garg | 46ad40b | 2022-07-12 12:42:10 +0530 | [diff] [blame] | 99 | { |
| 100 | return msm_pinctrl_functions[selector].val; |
| 101 | } |
| 102 | |
Caleb Connolly | 190005c | 2024-02-26 17:26:17 +0000 | [diff] [blame] | 103 | static const struct msm_pinctrl_data qcs404_data = { |
| 104 | .pin_data = { |
| 105 | .pin_count = 126, |
Caleb Connolly | ab6a1ac | 2024-02-26 17:26:18 +0000 | [diff] [blame] | 106 | .pin_offsets = qcs404_pin_offsets, |
Caleb Connolly | 190005c | 2024-02-26 17:26:17 +0000 | [diff] [blame] | 107 | .special_pins_start = 120, |
| 108 | }, |
Sumit Garg | 46ad40b | 2022-07-12 12:42:10 +0530 | [diff] [blame] | 109 | .functions_count = ARRAY_SIZE(msm_pinctrl_functions), |
| 110 | .get_function_name = qcs404_get_function_name, |
| 111 | .get_function_mux = qcs404_get_function_mux, |
| 112 | .get_pin_name = qcs404_get_pin_name, |
| 113 | }; |
Caleb Connolly | 506eb53 | 2023-11-14 12:55:40 +0000 | [diff] [blame] | 114 | |
| 115 | static const struct udevice_id msm_pinctrl_ids[] = { |
| 116 | { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data }, |
| 117 | { /* Sentinal */ } |
| 118 | }; |
| 119 | |
| 120 | U_BOOT_DRIVER(pinctrl_qcs404) = { |
| 121 | .name = "pinctrl_qcs404", |
| 122 | .id = UCLASS_NOP, |
| 123 | .of_match = msm_pinctrl_ids, |
| 124 | .ops = &msm_pinctrl_ops, |
| 125 | .bind = msm_pinctrl_bind, |
| 126 | }; |