blob: d6374a58e330a4d38778acbb1f8961489a889f01 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Thierry Reding412c7582014-12-09 22:25:12 -07002/*
3 * Copyright (c) 2010, CompuLab, Ltd.
4 * Author: Mike Rapoport <mike@compulab.co.il>
5 *
6 * Based on NVIDIA PCIe driver
7 * Copyright (c) 2008-2009, NVIDIA Corporation.
8 *
9 * Copyright (c) 2013-2014, NVIDIA Corporation.
Thierry Reding412c7582014-12-09 22:25:12 -070010 */
11
Thierry Reding412c7582014-12-09 22:25:12 -070012#define pr_fmt(fmt) "tegra-pcie: " fmt
13
Tom Riniabb9a042024-05-18 20:20:43 -060014#include <common.h>
Stephen Warren86f6a942016-08-05 16:10:34 -060015#include <clk.h>
Simon Glass46fcfc12015-11-19 20:27:02 -070016#include <dm.h>
Thierry Reding412c7582014-12-09 22:25:12 -070017#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060018#include <log.h>
Thierry Reding412c7582014-12-09 22:25:12 -070019#include <malloc.h>
20#include <pci.h>
Marcel Ziswiler53f48632018-05-08 17:34:09 +020021#include <pci_tegra.h>
Stephen Warren86f6a942016-08-05 16:10:34 -060022#include <power-domain.h>
23#include <reset.h>
Simon Glassdbd79542020-05-10 11:40:11 -060024#include <linux/delay.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060025#include <linux/printk.h>
Thierry Reding412c7582014-12-09 22:25:12 -070026
27#include <asm/io.h>
28#include <asm/gpio.h>
29
Simon Glasse6a30e02017-07-25 08:30:09 -060030#include <linux/ioport.h>
Stephen Warren86f6a942016-08-05 16:10:34 -060031#include <linux/list.h>
32
33#ifndef CONFIG_TEGRA186
Thierry Reding412c7582014-12-09 22:25:12 -070034#include <asm/arch/clock.h>
35#include <asm/arch/powergate.h>
36#include <asm/arch-tegra/xusb-padctl.h>
Thierry Reding412c7582014-12-09 22:25:12 -070037#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
Stephen Warren86f6a942016-08-05 16:10:34 -060038#endif
39
40/*
41 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
42 * should not be present. These are needed because newer Tegra SoCs support
43 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
44 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
45 * fixed to implement the standard APIs, and all drivers converted to solely
46 * use the new standard APIs, with no ifdefs.
47 */
Thierry Reding412c7582014-12-09 22:25:12 -070048
Thierry Reding412c7582014-12-09 22:25:12 -070049#define AFI_AXI_BAR0_SZ 0x00
50#define AFI_AXI_BAR1_SZ 0x04
51#define AFI_AXI_BAR2_SZ 0x08
52#define AFI_AXI_BAR3_SZ 0x0c
53#define AFI_AXI_BAR4_SZ 0x10
54#define AFI_AXI_BAR5_SZ 0x14
55
56#define AFI_AXI_BAR0_START 0x18
57#define AFI_AXI_BAR1_START 0x1c
58#define AFI_AXI_BAR2_START 0x20
59#define AFI_AXI_BAR3_START 0x24
60#define AFI_AXI_BAR4_START 0x28
61#define AFI_AXI_BAR5_START 0x2c
62
63#define AFI_FPCI_BAR0 0x30
64#define AFI_FPCI_BAR1 0x34
65#define AFI_FPCI_BAR2 0x38
66#define AFI_FPCI_BAR3 0x3c
67#define AFI_FPCI_BAR4 0x40
68#define AFI_FPCI_BAR5 0x44
69
70#define AFI_CACHE_BAR0_SZ 0x48
71#define AFI_CACHE_BAR0_ST 0x4c
72#define AFI_CACHE_BAR1_SZ 0x50
73#define AFI_CACHE_BAR1_ST 0x54
74
75#define AFI_MSI_BAR_SZ 0x60
76#define AFI_MSI_FPCI_BAR_ST 0x64
77#define AFI_MSI_AXI_BAR_ST 0x68
78
79#define AFI_CONFIGURATION 0xac
80#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
81
82#define AFI_FPCI_ERROR_MASKS 0xb0
83
84#define AFI_INTR_MASK 0xb4
85#define AFI_INTR_MASK_INT_MASK (1 << 0)
86#define AFI_INTR_MASK_MSI_MASK (1 << 8)
87
88#define AFI_SM_INTR_ENABLE 0xc4
89#define AFI_SM_INTR_INTA_ASSERT (1 << 0)
90#define AFI_SM_INTR_INTB_ASSERT (1 << 1)
91#define AFI_SM_INTR_INTC_ASSERT (1 << 2)
92#define AFI_SM_INTR_INTD_ASSERT (1 << 3)
93#define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
94#define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
95#define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
96#define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
97
98#define AFI_AFI_INTR_ENABLE 0xc8
99#define AFI_INTR_EN_INI_SLVERR (1 << 0)
100#define AFI_INTR_EN_INI_DECERR (1 << 1)
101#define AFI_INTR_EN_TGT_SLVERR (1 << 2)
102#define AFI_INTR_EN_TGT_DECERR (1 << 3)
103#define AFI_INTR_EN_TGT_WRERR (1 << 4)
104#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
105#define AFI_INTR_EN_AXI_DECERR (1 << 6)
106#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
107#define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
108
109#define AFI_PCIE_CONFIG 0x0f8
110#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
111#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
112#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
113#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
114#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
115#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
116#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
117#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
118#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
119#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
Stephen Warren86f6a942016-08-05 16:10:34 -0600120#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
121#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
122#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
Thierry Reding412c7582014-12-09 22:25:12 -0700123
124#define AFI_FUSE 0x104
125#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
126
127#define AFI_PEX0_CTRL 0x110
128#define AFI_PEX1_CTRL 0x118
129#define AFI_PEX2_CTRL 0x128
Stephen Warren86f6a942016-08-05 16:10:34 -0600130#define AFI_PEX2_CTRL_T186 0x19c
Thierry Reding412c7582014-12-09 22:25:12 -0700131#define AFI_PEX_CTRL_RST (1 << 0)
132#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
133#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
134#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
135
136#define AFI_PLLE_CONTROL 0x160
137#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
138#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
139
140#define AFI_PEXBIAS_CTRL_0 0x168
141
142#define PADS_CTL_SEL 0x0000009C
143
144#define PADS_CTL 0x000000A0
145#define PADS_CTL_IDDQ_1L (1 << 0)
146#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
147#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
148
149#define PADS_PLL_CTL_TEGRA20 0x000000B8
150#define PADS_PLL_CTL_TEGRA30 0x000000B4
151#define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
152#define PADS_PLL_CTL_LOCKDET (0x1 << 8)
153#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
154#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
155#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
156#define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
157#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
158#define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
159#define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
160#define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
161
162#define PADS_REFCLK_CFG0 0x000000C8
163#define PADS_REFCLK_CFG1 0x000000CC
164
165/*
166 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
167 * entries, one entry per PCIe port. These field definitions and desired
168 * values aren't in the TRM, but do come from NVIDIA.
169 */
170#define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
171#define PADS_REFCLK_CFG_E_TERM_SHIFT 7
172#define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
173#define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
174
Thierry Reding412c7582014-12-09 22:25:12 -0700175#define RP_VEND_XP 0x00000F00
176#define RP_VEND_XP_DL_UP (1 << 30)
177
Stephen Warrene3553be2015-10-05 17:00:42 -0600178#define RP_VEND_CTL2 0x00000FA8
179#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
180
Thierry Reding412c7582014-12-09 22:25:12 -0700181#define RP_PRIV_MISC 0x00000FE0
182#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
183#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
184
185#define RP_LINK_CONTROL_STATUS 0x00000090
186#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
187#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
188
Simon Glass46fcfc12015-11-19 20:27:02 -0700189enum tegra_pci_id {
190 TEGRA20_PCIE,
191 TEGRA30_PCIE,
192 TEGRA124_PCIE,
193 TEGRA210_PCIE,
Stephen Warren86f6a942016-08-05 16:10:34 -0600194 TEGRA186_PCIE,
Simon Glass46fcfc12015-11-19 20:27:02 -0700195};
Thierry Reding412c7582014-12-09 22:25:12 -0700196
197struct tegra_pcie_port {
198 struct tegra_pcie *pcie;
199
200 struct fdt_resource regs;
201 unsigned int num_lanes;
202 unsigned int index;
203
204 struct list_head list;
205};
206
207struct tegra_pcie_soc {
208 unsigned int num_ports;
209 unsigned long pads_pll_ctl;
210 unsigned long tx_ref_sel;
Stephen Warren86f6a942016-08-05 16:10:34 -0600211 unsigned long afi_pex2_ctrl;
Stephen Warrend132c472016-06-21 12:47:51 -0600212 u32 pads_refclk_cfg0;
213 u32 pads_refclk_cfg1;
Thierry Reding412c7582014-12-09 22:25:12 -0700214 bool has_pex_clkreq_en;
215 bool has_pex_bias_ctrl;
216 bool has_cml_clk;
217 bool has_gen2;
Stephen Warrene3553be2015-10-05 17:00:42 -0600218 bool force_pca_enable;
Thierry Reding412c7582014-12-09 22:25:12 -0700219};
220
221struct tegra_pcie {
Simon Glasse6a30e02017-07-25 08:30:09 -0600222 struct resource pads;
223 struct resource afi;
224 struct resource cs;
Thierry Reding412c7582014-12-09 22:25:12 -0700225
Thierry Reding412c7582014-12-09 22:25:12 -0700226 struct list_head ports;
227 unsigned long xbar;
228
229 const struct tegra_pcie_soc *soc;
Stephen Warren86f6a942016-08-05 16:10:34 -0600230
231#ifdef CONFIG_TEGRA186
232 struct clk clk_afi;
233 struct clk clk_pex;
234 struct reset_ctl reset_afi;
235 struct reset_ctl reset_pex;
236 struct reset_ctl reset_pcie_x;
237 struct power_domain pwrdom;
238#else
Thierry Reding412c7582014-12-09 22:25:12 -0700239 struct tegra_xusb_phy *phy;
Stephen Warren86f6a942016-08-05 16:10:34 -0600240#endif
Thierry Reding412c7582014-12-09 22:25:12 -0700241};
242
Thierry Reding412c7582014-12-09 22:25:12 -0700243static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
244 unsigned long offset)
245{
246 writel(value, pcie->afi.start + offset);
247}
248
249static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
250{
251 return readl(pcie->afi.start + offset);
252}
253
254static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
255 unsigned long offset)
256{
257 writel(value, pcie->pads.start + offset);
258}
259
Stephen Warren86f6a942016-08-05 16:10:34 -0600260#ifndef CONFIG_TEGRA186
Thierry Reding412c7582014-12-09 22:25:12 -0700261static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
262{
263 return readl(pcie->pads.start + offset);
264}
Stephen Warren86f6a942016-08-05 16:10:34 -0600265#endif
Thierry Reding412c7582014-12-09 22:25:12 -0700266
267static unsigned long rp_readl(struct tegra_pcie_port *port,
268 unsigned long offset)
269{
270 return readl(port->regs.start + offset);
271}
272
273static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
274 unsigned long offset)
275{
276 writel(value, port->regs.start + offset);
277}
278
Thierry Reding412c7582014-12-09 22:25:12 -0700279static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
280 int where, unsigned long *address)
281{
282 unsigned int bus = PCI_BUS(bdf);
283
284 if (bus == 0) {
285 unsigned int dev = PCI_DEV(bdf);
286 struct tegra_pcie_port *port;
287
288 list_for_each_entry(port, &pcie->ports, list) {
289 if (port->index + 1 == dev) {
290 *address = port->regs.start + (where & ~3);
291 return 0;
292 }
293 }
Stephen Warrenbbe71b22016-04-20 15:46:50 -0600294 return -EFAULT;
Thierry Reding412c7582014-12-09 22:25:12 -0700295 } else {
Stephen Warrenbbe71b22016-04-20 15:46:50 -0600296#ifdef CONFIG_TEGRA20
297 unsigned int dev = PCI_DEV(bdf);
298 if (dev != 0)
299 return -EFAULT;
300#endif
301
Pali Rohár63e37ad2021-11-26 11:42:46 +0100302 *address = pcie->cs.start +
303 (PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf),
304 PCI_FUNC(bdf), where) & ~PCI_CONF1_ENABLE);
Thierry Reding412c7582014-12-09 22:25:12 -0700305 return 0;
306 }
Thierry Reding412c7582014-12-09 22:25:12 -0700307}
308
Simon Glass2a311e82020-01-27 08:49:37 -0700309static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf,
Simon Glass46fcfc12015-11-19 20:27:02 -0700310 uint offset, ulong *valuep,
311 enum pci_size_t size)
Thierry Reding412c7582014-12-09 22:25:12 -0700312{
Simon Glass46fcfc12015-11-19 20:27:02 -0700313 struct tegra_pcie *pcie = dev_get_priv(bus);
314 unsigned long address, value;
Thierry Reding412c7582014-12-09 22:25:12 -0700315 int err;
316
Simon Glass46fcfc12015-11-19 20:27:02 -0700317 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
Thierry Reding412c7582014-12-09 22:25:12 -0700318 if (err < 0) {
Simon Glass46fcfc12015-11-19 20:27:02 -0700319 value = 0xffffffff;
320 goto done;
Thierry Reding412c7582014-12-09 22:25:12 -0700321 }
322
Simon Glass46fcfc12015-11-19 20:27:02 -0700323 value = readl(address);
Thierry Reding412c7582014-12-09 22:25:12 -0700324
Stephen Warrenbbe71b22016-04-20 15:46:50 -0600325#ifdef CONFIG_TEGRA20
Thierry Reding412c7582014-12-09 22:25:12 -0700326 /* fixup root port class */
327 if (PCI_BUS(bdf) == 0) {
Stephen Warrenbbe71b22016-04-20 15:46:50 -0600328 if ((offset & ~3) == PCI_CLASS_REVISION) {
Pali Rohár25781e22022-02-18 13:18:40 +0100329 value &= ~0x00ffff00;
330 value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
Thierry Reding412c7582014-12-09 22:25:12 -0700331 }
332 }
Stephen Warrenbbe71b22016-04-20 15:46:50 -0600333#endif
Thierry Reding412c7582014-12-09 22:25:12 -0700334
Simon Glass46fcfc12015-11-19 20:27:02 -0700335done:
336 *valuep = pci_conv_32_to_size(value, offset, size);
337
Thierry Reding412c7582014-12-09 22:25:12 -0700338 return 0;
339}
340
Simon Glass46fcfc12015-11-19 20:27:02 -0700341static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
342 uint offset, ulong value,
343 enum pci_size_t size)
Thierry Reding412c7582014-12-09 22:25:12 -0700344{
Simon Glass46fcfc12015-11-19 20:27:02 -0700345 struct tegra_pcie *pcie = dev_get_priv(bus);
Thierry Reding412c7582014-12-09 22:25:12 -0700346 unsigned long address;
Simon Glass46fcfc12015-11-19 20:27:02 -0700347 ulong old;
Thierry Reding412c7582014-12-09 22:25:12 -0700348 int err;
349
Simon Glass46fcfc12015-11-19 20:27:02 -0700350 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
Thierry Reding412c7582014-12-09 22:25:12 -0700351 if (err < 0)
Simon Glass46fcfc12015-11-19 20:27:02 -0700352 return 0;
Thierry Reding412c7582014-12-09 22:25:12 -0700353
Simon Glass46fcfc12015-11-19 20:27:02 -0700354 old = readl(address);
355 value = pci_conv_size_to_32(old, value, offset, size);
Thierry Reding412c7582014-12-09 22:25:12 -0700356 writel(value, address);
357
358 return 0;
359}
360
Simon Glasse6a30e02017-07-25 08:30:09 -0600361static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port)
Thierry Reding412c7582014-12-09 22:25:12 -0700362{
363 const u32 *addr;
364 int len;
365
Simon Glasse6a30e02017-07-25 08:30:09 -0600366 addr = ofnode_get_property(node, "assigned-addresses", &len);
Thierry Reding412c7582014-12-09 22:25:12 -0700367 if (!addr) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900368 pr_err("property \"assigned-addresses\" not found");
Thierry Reding412c7582014-12-09 22:25:12 -0700369 return -FDT_ERR_NOTFOUND;
370 }
371
372 port->regs.start = fdt32_to_cpu(addr[2]);
373 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
374
375 return 0;
376}
377
Simon Glasse6a30e02017-07-25 08:30:09 -0600378static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
Simon Glass46fcfc12015-11-19 20:27:02 -0700379 enum tegra_pci_id id, unsigned long *xbar)
Thierry Reding412c7582014-12-09 22:25:12 -0700380{
Thierry Reding412c7582014-12-09 22:25:12 -0700381 switch (id) {
Simon Glass46fcfc12015-11-19 20:27:02 -0700382 case TEGRA20_PCIE:
Thierry Reding412c7582014-12-09 22:25:12 -0700383 switch (lanes) {
384 case 0x00000004:
385 debug("single-mode configuration\n");
386 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
387 return 0;
388
389 case 0x00000202:
390 debug("dual-mode configuration\n");
391 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
392 return 0;
393 }
394 break;
Simon Glass46fcfc12015-11-19 20:27:02 -0700395 case TEGRA30_PCIE:
Thierry Reding412c7582014-12-09 22:25:12 -0700396 switch (lanes) {
397 case 0x00000204:
398 debug("4x1, 2x1 configuration\n");
399 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
400 return 0;
401
402 case 0x00020202:
403 debug("2x3 configuration\n");
404 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
405 return 0;
406
407 case 0x00010104:
408 debug("4x1, 1x2 configuration\n");
409 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
410 return 0;
411 }
412 break;
Simon Glass46fcfc12015-11-19 20:27:02 -0700413 case TEGRA124_PCIE:
414 case TEGRA210_PCIE:
Thierry Reding412c7582014-12-09 22:25:12 -0700415 switch (lanes) {
416 case 0x0000104:
417 debug("4x1, 1x1 configuration\n");
418 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
419 return 0;
420
421 case 0x0000102:
422 debug("2x1, 1x1 configuration\n");
423 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
424 return 0;
425 }
426 break;
Stephen Warren86f6a942016-08-05 16:10:34 -0600427 case TEGRA186_PCIE:
428 switch (lanes) {
429 case 0x0010004:
430 debug("x4 x1 configuration\n");
431 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
432 return 0;
433
434 case 0x0010102:
435 debug("x2 x1 x1 configuration\n");
436 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
437 return 0;
438
439 case 0x0010101:
440 debug("x1 x1 x1 configuration\n");
441 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
442 return 0;
443 }
444 break;
Thierry Reding412c7582014-12-09 22:25:12 -0700445 default:
446 break;
447 }
448
449 return -FDT_ERR_NOTFOUND;
450}
451
Simon Glasse6a30e02017-07-25 08:30:09 -0600452static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
Thierry Reding412c7582014-12-09 22:25:12 -0700453{
Bin Meng779847e2014-12-31 16:05:11 +0800454 struct fdt_pci_addr addr;
Thierry Reding412c7582014-12-09 22:25:12 -0700455 int err;
456
Simon Glasse6a30e02017-07-25 08:30:09 -0600457 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
Thierry Reding412c7582014-12-09 22:25:12 -0700458 if (err < 0) {
Peter Robinsonb1f92722022-05-03 09:29:22 +0100459 pr_err("failed to parse \"nvidia,num-lanes\" property\n");
Thierry Reding412c7582014-12-09 22:25:12 -0700460 return err;
461 }
462
463 *lanes = err;
464
Simon Glass4289c262023-09-26 08:14:58 -0600465 err = ofnode_read_pci_addr(node, 0, "reg", &addr, NULL);
Thierry Reding412c7582014-12-09 22:25:12 -0700466 if (err < 0) {
Peter Robinsonb1f92722022-05-03 09:29:22 +0100467 pr_err("failed to parse \"reg\" property\n");
Thierry Reding412c7582014-12-09 22:25:12 -0700468 return err;
469 }
470
Sjoerd Simonse3c64172015-01-20 18:06:53 +0100471 *index = PCI_DEV(addr.phys_hi) - 1;
Thierry Reding412c7582014-12-09 22:25:12 -0700472
473 return 0;
474}
475
Simon Glass46fcfc12015-11-19 20:27:02 -0700476int __weak tegra_pcie_board_init(void)
477{
478 return 0;
479}
480
Simon Glasse6a30e02017-07-25 08:30:09 -0600481static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id,
Thierry Reding412c7582014-12-09 22:25:12 -0700482 struct tegra_pcie *pcie)
483{
Simon Glasse6a30e02017-07-25 08:30:09 -0600484 ofnode subnode;
Thierry Reding412c7582014-12-09 22:25:12 -0700485 u32 lanes = 0;
Simon Glasse6a30e02017-07-25 08:30:09 -0600486 int err;
Thierry Reding412c7582014-12-09 22:25:12 -0700487
Simon Glasse6a30e02017-07-25 08:30:09 -0600488 err = dev_read_resource(dev, 0, &pcie->pads);
Thierry Reding412c7582014-12-09 22:25:12 -0700489 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900490 pr_err("resource \"pads\" not found");
Thierry Reding412c7582014-12-09 22:25:12 -0700491 return err;
492 }
493
Simon Glasse6a30e02017-07-25 08:30:09 -0600494 err = dev_read_resource(dev, 1, &pcie->afi);
Thierry Reding412c7582014-12-09 22:25:12 -0700495 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900496 pr_err("resource \"afi\" not found");
Thierry Reding412c7582014-12-09 22:25:12 -0700497 return err;
498 }
499
Simon Glasse6a30e02017-07-25 08:30:09 -0600500 err = dev_read_resource(dev, 2, &pcie->cs);
Thierry Reding412c7582014-12-09 22:25:12 -0700501 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900502 pr_err("resource \"cs\" not found");
Thierry Reding412c7582014-12-09 22:25:12 -0700503 return err;
504 }
505
Simon Glasse49f4952016-01-17 14:51:55 -0700506 err = tegra_pcie_board_init();
507 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900508 pr_err("tegra_pcie_board_init() failed: err=%d", err);
Simon Glasse49f4952016-01-17 14:51:55 -0700509 return err;
510 }
Simon Glass46fcfc12015-11-19 20:27:02 -0700511
Stephen Warren86f6a942016-08-05 16:10:34 -0600512#ifndef CONFIG_TEGRA186
Thierry Reding412c7582014-12-09 22:25:12 -0700513 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
514 if (pcie->phy) {
515 err = tegra_xusb_phy_prepare(pcie->phy);
516 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900517 pr_err("failed to prepare PHY: %d", err);
Thierry Reding412c7582014-12-09 22:25:12 -0700518 return err;
519 }
520 }
Stephen Warren86f6a942016-08-05 16:10:34 -0600521#endif
Thierry Reding412c7582014-12-09 22:25:12 -0700522
Simon Glasse6a30e02017-07-25 08:30:09 -0600523 dev_for_each_subnode(subnode, dev) {
Thierry Reding412c7582014-12-09 22:25:12 -0700524 unsigned int index = 0, num_lanes = 0;
525 struct tegra_pcie_port *port;
526
Simon Glasse6a30e02017-07-25 08:30:09 -0600527 err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes);
Thierry Reding412c7582014-12-09 22:25:12 -0700528 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900529 pr_err("failed to obtain root port info");
Thierry Reding412c7582014-12-09 22:25:12 -0700530 continue;
531 }
532
533 lanes |= num_lanes << (index << 3);
534
Simon Glass2e4938b2022-09-06 20:27:17 -0600535 if (!ofnode_is_enabled(subnode))
Thierry Reding412c7582014-12-09 22:25:12 -0700536 continue;
537
538 port = malloc(sizeof(*port));
539 if (!port)
540 continue;
541
542 memset(port, 0, sizeof(*port));
543 port->num_lanes = num_lanes;
544 port->index = index;
545
Simon Glasse6a30e02017-07-25 08:30:09 -0600546 err = tegra_pcie_port_parse_dt(subnode, port);
Thierry Reding412c7582014-12-09 22:25:12 -0700547 if (err < 0) {
548 free(port);
549 continue;
550 }
551
552 list_add_tail(&port->list, &pcie->ports);
553 port->pcie = pcie;
554 }
555
Simon Glasse6a30e02017-07-25 08:30:09 -0600556 err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id,
557 &pcie->xbar);
Thierry Reding412c7582014-12-09 22:25:12 -0700558 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900559 pr_err("invalid lane configuration");
Thierry Reding412c7582014-12-09 22:25:12 -0700560 return err;
561 }
562
Thierry Reding412c7582014-12-09 22:25:12 -0700563 return 0;
564}
565
Stephen Warren86f6a942016-08-05 16:10:34 -0600566#ifdef CONFIG_TEGRA186
567static int tegra_pcie_power_on(struct tegra_pcie *pcie)
568{
569 int ret;
570
571 ret = power_domain_on(&pcie->pwrdom);
572 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900573 pr_err("power_domain_on() failed: %d\n", ret);
Stephen Warren86f6a942016-08-05 16:10:34 -0600574 return ret;
575 }
576
577 ret = clk_enable(&pcie->clk_afi);
578 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900579 pr_err("clk_enable(afi) failed: %d\n", ret);
Stephen Warren86f6a942016-08-05 16:10:34 -0600580 return ret;
581 }
582
583 ret = clk_enable(&pcie->clk_pex);
584 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900585 pr_err("clk_enable(pex) failed: %d\n", ret);
Stephen Warren86f6a942016-08-05 16:10:34 -0600586 return ret;
587 }
588
589 ret = reset_deassert(&pcie->reset_afi);
590 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900591 pr_err("reset_deassert(afi) failed: %d\n", ret);
Stephen Warren86f6a942016-08-05 16:10:34 -0600592 return ret;
593 }
594
595 ret = reset_deassert(&pcie->reset_pex);
596 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900597 pr_err("reset_deassert(pex) failed: %d\n", ret);
Stephen Warren86f6a942016-08-05 16:10:34 -0600598 return ret;
599 }
600
601 return 0;
602}
603#else
Thierry Reding412c7582014-12-09 22:25:12 -0700604static int tegra_pcie_power_on(struct tegra_pcie *pcie)
605{
606 const struct tegra_pcie_soc *soc = pcie->soc;
607 unsigned long value;
608 int err;
609
610 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
611 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
612 reset_set_enable(PERIPH_ID_AFI, 1);
613 reset_set_enable(PERIPH_ID_PCIE, 1);
614
615 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
616 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900617 pr_err("failed to power off PCIe partition: %d", err);
Thierry Reding412c7582014-12-09 22:25:12 -0700618 return err;
619 }
620
Thierry Reding412c7582014-12-09 22:25:12 -0700621 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
622 PERIPH_ID_PCIE);
623 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900624 pr_err("failed to power up PCIe partition: %d", err);
Thierry Reding412c7582014-12-09 22:25:12 -0700625 return err;
626 }
627
628 /* take AFI controller out of reset */
629 reset_set_enable(PERIPH_ID_AFI, 0);
630
631 /* enable AFI clock */
632 clock_enable(PERIPH_ID_AFI);
633
634 if (soc->has_cml_clk) {
635 /* enable CML clock */
636 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
637 value |= (1 << 0);
638 value &= ~(1 << 1);
639 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
640 }
641
642 err = tegra_plle_enable();
643 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900644 pr_err("failed to enable PLLE: %d\n", err);
Thierry Reding412c7582014-12-09 22:25:12 -0700645 return err;
646 }
647
648 return 0;
649}
650
651static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
652{
653 const struct tegra_pcie_soc *soc = pcie->soc;
654 unsigned long start = get_timer(0);
655 u32 value;
656
657 while (get_timer(start) < timeout) {
658 value = pads_readl(pcie, soc->pads_pll_ctl);
659 if (value & PADS_PLL_CTL_LOCKDET)
660 return 0;
661 }
662
663 return -ETIMEDOUT;
664}
665
666static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
667{
668 const struct tegra_pcie_soc *soc = pcie->soc;
669 u32 value;
670 int err;
671
672 /* initialize internal PHY, enable up to 16 PCIe lanes */
673 pads_writel(pcie, 0, PADS_CTL_SEL);
674
675 /* override IDDQ to 1 on all 4 lanes */
676 value = pads_readl(pcie, PADS_CTL);
677 value |= PADS_CTL_IDDQ_1L;
678 pads_writel(pcie, value, PADS_CTL);
679
680 /*
681 * Set up PHY PLL inputs select PLLE output as refclock, set TX
682 * ref sel to div10 (not div5).
683 */
684 value = pads_readl(pcie, soc->pads_pll_ctl);
685 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
686 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
687 pads_writel(pcie, value, soc->pads_pll_ctl);
688
689 /* reset PLL */
690 value = pads_readl(pcie, soc->pads_pll_ctl);
691 value &= ~PADS_PLL_CTL_RST_B4SM;
692 pads_writel(pcie, value, soc->pads_pll_ctl);
693
694 udelay(20);
695
696 /* take PLL out of reset */
697 value = pads_readl(pcie, soc->pads_pll_ctl);
698 value |= PADS_PLL_CTL_RST_B4SM;
699 pads_writel(pcie, value, soc->pads_pll_ctl);
700
Thierry Reding412c7582014-12-09 22:25:12 -0700701 /* wait for the PLL to lock */
702 err = tegra_pcie_pll_wait(pcie, 500);
703 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900704 pr_err("PLL failed to lock: %d", err);
Thierry Reding412c7582014-12-09 22:25:12 -0700705 return err;
706 }
707
708 /* turn off IDDQ override */
709 value = pads_readl(pcie, PADS_CTL);
710 value &= ~PADS_CTL_IDDQ_1L;
711 pads_writel(pcie, value, PADS_CTL);
712
713 /* enable TX/RX data */
714 value = pads_readl(pcie, PADS_CTL);
715 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
716 pads_writel(pcie, value, PADS_CTL);
717
718 return 0;
719}
Stephen Warren86f6a942016-08-05 16:10:34 -0600720#endif
Thierry Reding412c7582014-12-09 22:25:12 -0700721
722static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
723{
724 const struct tegra_pcie_soc *soc = pcie->soc;
725 struct tegra_pcie_port *port;
726 u32 value;
727 int err;
728
Stephen Warren86f6a942016-08-05 16:10:34 -0600729#ifdef CONFIG_TEGRA186
730 {
731#else
Thierry Reding412c7582014-12-09 22:25:12 -0700732 if (pcie->phy) {
Stephen Warren86f6a942016-08-05 16:10:34 -0600733#endif
Thierry Reding412c7582014-12-09 22:25:12 -0700734 value = afi_readl(pcie, AFI_PLLE_CONTROL);
735 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
736 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
737 afi_writel(pcie, value, AFI_PLLE_CONTROL);
738 }
739
740 if (soc->has_pex_bias_ctrl)
741 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
742
743 value = afi_readl(pcie, AFI_PCIE_CONFIG);
744 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
745 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
746
747 list_for_each_entry(port, &pcie->ports, list)
748 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
749
750 afi_writel(pcie, value, AFI_PCIE_CONFIG);
751
752 value = afi_readl(pcie, AFI_FUSE);
753
754 if (soc->has_gen2)
755 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
756 else
757 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
758
759 afi_writel(pcie, value, AFI_FUSE);
760
Stephen Warren86f6a942016-08-05 16:10:34 -0600761#ifndef CONFIG_TEGRA186
Thierry Reding412c7582014-12-09 22:25:12 -0700762 if (pcie->phy)
763 err = tegra_xusb_phy_enable(pcie->phy);
764 else
765 err = tegra_pcie_phy_enable(pcie);
766
767 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900768 pr_err("failed to power on PHY: %d\n", err);
Thierry Reding412c7582014-12-09 22:25:12 -0700769 return err;
770 }
Stephen Warren86f6a942016-08-05 16:10:34 -0600771#endif
Thierry Reding412c7582014-12-09 22:25:12 -0700772
773 /* take the PCIEXCLK logic out of reset */
Stephen Warren86f6a942016-08-05 16:10:34 -0600774#ifdef CONFIG_TEGRA186
775 err = reset_deassert(&pcie->reset_pcie_x);
776 if (err) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900777 pr_err("reset_deassert(pcie_x) failed: %d\n", err);
Stephen Warren86f6a942016-08-05 16:10:34 -0600778 return err;
779 }
780#else
Thierry Reding412c7582014-12-09 22:25:12 -0700781 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
Stephen Warren86f6a942016-08-05 16:10:34 -0600782#endif
Thierry Reding412c7582014-12-09 22:25:12 -0700783
784 /* finally enable PCIe */
785 value = afi_readl(pcie, AFI_CONFIGURATION);
786 value |= AFI_CONFIGURATION_EN_FPCI;
787 afi_writel(pcie, value, AFI_CONFIGURATION);
788
789 /* disable all interrupts */
790 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
791 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
792 afi_writel(pcie, 0, AFI_INTR_MASK);
793 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
794
795 return 0;
796}
797
Simon Glass46fcfc12015-11-19 20:27:02 -0700798static int tegra_pcie_setup_translations(struct udevice *bus)
Thierry Reding412c7582014-12-09 22:25:12 -0700799{
Simon Glass46fcfc12015-11-19 20:27:02 -0700800 struct tegra_pcie *pcie = dev_get_priv(bus);
Thierry Reding412c7582014-12-09 22:25:12 -0700801 unsigned long fpci, axi, size;
Simon Glass46fcfc12015-11-19 20:27:02 -0700802 struct pci_region *io, *mem, *pref;
803 int count;
Thierry Reding412c7582014-12-09 22:25:12 -0700804
805 /* BAR 0: type 1 extended configuration space */
806 fpci = 0xfe100000;
Simon Glasse6a30e02017-07-25 08:30:09 -0600807 size = resource_size(&pcie->cs);
Thierry Reding412c7582014-12-09 22:25:12 -0700808 axi = pcie->cs.start;
809
810 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
811 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
812 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
813
Simon Glass46fcfc12015-11-19 20:27:02 -0700814 count = pci_get_regions(bus, &io, &mem, &pref);
815 if (count != 3)
816 return -EINVAL;
817
Thierry Reding412c7582014-12-09 22:25:12 -0700818 /* BAR 1: downstream I/O */
819 fpci = 0xfdfc0000;
Simon Glass46fcfc12015-11-19 20:27:02 -0700820 size = io->size;
821 axi = io->phys_start;
Thierry Reding412c7582014-12-09 22:25:12 -0700822
823 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
824 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
825 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
826
827 /* BAR 2: prefetchable memory */
Simon Glass46fcfc12015-11-19 20:27:02 -0700828 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
829 size = pref->size;
830 axi = pref->phys_start;
Thierry Reding412c7582014-12-09 22:25:12 -0700831
832 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
833 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
834 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
835
836 /* BAR 3: non-prefetchable memory */
Simon Glass46fcfc12015-11-19 20:27:02 -0700837 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
838 size = mem->size;
839 axi = mem->phys_start;
Thierry Reding412c7582014-12-09 22:25:12 -0700840
841 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
842 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
843 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
844
845 /* NULL out the remaining BARs as they are not used */
846 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
847 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
848 afi_writel(pcie, 0, AFI_FPCI_BAR4);
849
850 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
851 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
852 afi_writel(pcie, 0, AFI_FPCI_BAR5);
853
854 /* map all upstream transactions as uncached */
855 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
856 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
857 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
858 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
859
860 /* MSI translations are setup only when needed */
861 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
862 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
863 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
864 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
Simon Glass46fcfc12015-11-19 20:27:02 -0700865
866 return 0;
Thierry Reding412c7582014-12-09 22:25:12 -0700867}
868
869static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
870{
871 unsigned long ret = 0;
872
873 switch (port->index) {
874 case 0:
875 ret = AFI_PEX0_CTRL;
876 break;
877
878 case 1:
879 ret = AFI_PEX1_CTRL;
880 break;
881
882 case 2:
Stephen Warren86f6a942016-08-05 16:10:34 -0600883 ret = port->pcie->soc->afi_pex2_ctrl;
Thierry Reding412c7582014-12-09 22:25:12 -0700884 break;
885 }
886
887 return ret;
888}
889
Marcel Ziswiler53f48632018-05-08 17:34:09 +0200890void tegra_pcie_port_reset(struct tegra_pcie_port *port)
Thierry Reding412c7582014-12-09 22:25:12 -0700891{
892 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
893 unsigned long value;
894
895 /* pulse reset signel */
896 value = afi_readl(port->pcie, ctrl);
897 value &= ~AFI_PEX_CTRL_RST;
898 afi_writel(port->pcie, value, ctrl);
899
900 udelay(2000);
901
902 value = afi_readl(port->pcie, ctrl);
903 value |= AFI_PEX_CTRL_RST;
904 afi_writel(port->pcie, value, ctrl);
905}
906
Marcel Ziswiler53f48632018-05-08 17:34:09 +0200907int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port)
908{
909 return port->index;
910}
911
912void __weak tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
913{
914 tegra_pcie_port_reset(port);
915}
916
Thierry Reding412c7582014-12-09 22:25:12 -0700917static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
918{
Stephen Warren29f49fc2016-06-24 08:36:04 -0600919 struct tegra_pcie *pcie = port->pcie;
920 const struct tegra_pcie_soc *soc = pcie->soc;
Thierry Reding412c7582014-12-09 22:25:12 -0700921 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
922 unsigned long value;
923
924 /* enable reference clock */
Stephen Warren29f49fc2016-06-24 08:36:04 -0600925 value = afi_readl(pcie, ctrl);
Thierry Reding412c7582014-12-09 22:25:12 -0700926 value |= AFI_PEX_CTRL_REFCLK_EN;
927
Stephen Warren29f49fc2016-06-24 08:36:04 -0600928 if (pcie->soc->has_pex_clkreq_en)
Thierry Reding412c7582014-12-09 22:25:12 -0700929 value |= AFI_PEX_CTRL_CLKREQ_EN;
930
931 value |= AFI_PEX_CTRL_OVERRIDE_EN;
932
Stephen Warren29f49fc2016-06-24 08:36:04 -0600933 afi_writel(pcie, value, ctrl);
Thierry Reding412c7582014-12-09 22:25:12 -0700934
Marcel Ziswiler53f48632018-05-08 17:34:09 +0200935 tegra_pcie_board_port_reset(port);
Stephen Warrene3553be2015-10-05 17:00:42 -0600936
937 if (soc->force_pca_enable) {
938 value = rp_readl(port, RP_VEND_CTL2);
939 value |= RP_VEND_CTL2_PCA_ENABLE;
940 rp_writel(port, value, RP_VEND_CTL2);
941 }
Stephen Warren29f49fc2016-06-24 08:36:04 -0600942
943 /* configure the reference clock driver */
944 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
945 if (soc->num_ports > 2)
946 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
Thierry Reding412c7582014-12-09 22:25:12 -0700947}
948
949static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
950{
951 unsigned int retries = 3;
952 unsigned long value;
953
954 value = rp_readl(port, RP_PRIV_MISC);
955 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
956 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
957 rp_writel(port, value, RP_PRIV_MISC);
958
959 do {
960 unsigned int timeout = 200;
961
962 do {
963 value = rp_readl(port, RP_VEND_XP);
964 if (value & RP_VEND_XP_DL_UP)
965 break;
966
967 udelay(2000);
968 } while (--timeout);
969
970 if (!timeout) {
971 debug("link %u down, retrying\n", port->index);
972 goto retry;
973 }
974
975 timeout = 200;
976
977 do {
978 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
979 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
980 return true;
981
982 udelay(2000);
983 } while (--timeout);
984
985retry:
Marcel Ziswiler53f48632018-05-08 17:34:09 +0200986 tegra_pcie_board_port_reset(port);
Thierry Reding412c7582014-12-09 22:25:12 -0700987 } while (--retries);
988
989 return false;
990}
991
992static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
993{
994 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
995 unsigned long value;
996
997 /* assert port reset */
998 value = afi_readl(port->pcie, ctrl);
999 value &= ~AFI_PEX_CTRL_RST;
1000 afi_writel(port->pcie, value, ctrl);
1001
1002 /* disable reference clock */
1003 value = afi_readl(port->pcie, ctrl);
1004 value &= ~AFI_PEX_CTRL_REFCLK_EN;
1005 afi_writel(port->pcie, value, ctrl);
1006}
1007
1008static void tegra_pcie_port_free(struct tegra_pcie_port *port)
1009{
1010 list_del(&port->list);
1011 free(port);
1012}
1013
1014static int tegra_pcie_enable(struct tegra_pcie *pcie)
1015{
1016 struct tegra_pcie_port *port, *tmp;
1017
1018 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1019 debug("probing port %u, using %u lanes\n", port->index,
1020 port->num_lanes);
1021
1022 tegra_pcie_port_enable(port);
1023
1024 if (tegra_pcie_port_check_link(port))
1025 continue;
1026
1027 debug("link %u down, ignoring\n", port->index);
1028
1029 tegra_pcie_port_disable(port);
1030 tegra_pcie_port_free(port);
1031 }
1032
1033 return 0;
1034}
1035
Simon Glass46fcfc12015-11-19 20:27:02 -07001036static const struct tegra_pcie_soc pci_tegra_soc[] = {
1037 [TEGRA20_PCIE] = {
1038 .num_ports = 2,
1039 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1040 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
Stephen Warrend132c472016-06-21 12:47:51 -06001041 .pads_refclk_cfg0 = 0xfa5cfa5c,
Simon Glass46fcfc12015-11-19 20:27:02 -07001042 .has_pex_clkreq_en = false,
1043 .has_pex_bias_ctrl = false,
1044 .has_cml_clk = false,
1045 .has_gen2 = false,
1046 },
1047 [TEGRA30_PCIE] = {
1048 .num_ports = 3,
1049 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1050 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
Stephen Warren86f6a942016-08-05 16:10:34 -06001051 .afi_pex2_ctrl = AFI_PEX2_CTRL,
Stephen Warrend132c472016-06-21 12:47:51 -06001052 .pads_refclk_cfg0 = 0xfa5cfa5c,
1053 .pads_refclk_cfg1 = 0xfa5cfa5c,
Simon Glass46fcfc12015-11-19 20:27:02 -07001054 .has_pex_clkreq_en = true,
1055 .has_pex_bias_ctrl = true,
1056 .has_cml_clk = true,
1057 .has_gen2 = false,
1058 },
1059 [TEGRA124_PCIE] = {
1060 .num_ports = 2,
1061 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1062 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
Stephen Warrend132c472016-06-21 12:47:51 -06001063 .pads_refclk_cfg0 = 0x44ac44ac,
Simon Glass46fcfc12015-11-19 20:27:02 -07001064 .has_pex_clkreq_en = true,
1065 .has_pex_bias_ctrl = true,
1066 .has_cml_clk = true,
1067 .has_gen2 = true,
1068 },
1069 [TEGRA210_PCIE] = {
1070 .num_ports = 2,
1071 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1072 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
Stephen Warrend132c472016-06-21 12:47:51 -06001073 .pads_refclk_cfg0 = 0x90b890b8,
Simon Glass46fcfc12015-11-19 20:27:02 -07001074 .has_pex_clkreq_en = true,
1075 .has_pex_bias_ctrl = true,
1076 .has_cml_clk = true,
1077 .has_gen2 = true,
1078 .force_pca_enable = true,
Stephen Warren86f6a942016-08-05 16:10:34 -06001079 },
1080 [TEGRA186_PCIE] = {
1081 .num_ports = 3,
1082 .afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
1083 .pads_refclk_cfg0 = 0x80b880b8,
1084 .pads_refclk_cfg1 = 0x000480b8,
1085 .has_pex_clkreq_en = true,
1086 .has_pex_bias_ctrl = true,
1087 .has_gen2 = true,
1088 },
Stephen Warren5e44dce2015-10-05 17:00:44 -06001089};
1090
Simon Glassaad29ae2020-12-03 16:55:21 -07001091static int pci_tegra_of_to_plat(struct udevice *dev)
Thierry Reding412c7582014-12-09 22:25:12 -07001092{
Simon Glass46fcfc12015-11-19 20:27:02 -07001093 struct tegra_pcie *pcie = dev_get_priv(dev);
1094 enum tegra_pci_id id;
Thierry Reding412c7582014-12-09 22:25:12 -07001095
Simon Glass46fcfc12015-11-19 20:27:02 -07001096 id = dev_get_driver_data(dev);
1097 pcie->soc = &pci_tegra_soc[id];
Thierry Reding412c7582014-12-09 22:25:12 -07001098
Simon Glass46fcfc12015-11-19 20:27:02 -07001099 INIT_LIST_HEAD(&pcie->ports);
Thierry Reding412c7582014-12-09 22:25:12 -07001100
Simon Glasse6a30e02017-07-25 08:30:09 -06001101 if (tegra_pcie_parse_dt(dev, id, pcie))
Simon Glass46fcfc12015-11-19 20:27:02 -07001102 return -EINVAL;
Thierry Reding412c7582014-12-09 22:25:12 -07001103
Simon Glass46fcfc12015-11-19 20:27:02 -07001104 return 0;
1105}
Thierry Reding412c7582014-12-09 22:25:12 -07001106
Simon Glass46fcfc12015-11-19 20:27:02 -07001107static int pci_tegra_probe(struct udevice *dev)
1108{
1109 struct tegra_pcie *pcie = dev_get_priv(dev);
1110 int err;
Thierry Reding412c7582014-12-09 22:25:12 -07001111
Stephen Warren86f6a942016-08-05 16:10:34 -06001112#ifdef CONFIG_TEGRA186
1113 err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
1114 if (err) {
1115 debug("clk_get_by_name(afi) failed: %d\n", err);
1116 return err;
1117 }
1118
1119 err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
1120 if (err) {
1121 debug("clk_get_by_name(pex) failed: %d\n", err);
1122 return err;
1123 }
1124
1125 err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
1126 if (err) {
1127 debug("reset_get_by_name(afi) failed: %d\n", err);
1128 return err;
1129 }
1130
1131 err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
1132 if (err) {
1133 debug("reset_get_by_name(pex) failed: %d\n", err);
1134 return err;
1135 }
1136
1137 err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
1138 if (err) {
1139 debug("reset_get_by_name(pcie_x) failed: %d\n", err);
1140 return err;
1141 }
1142
1143 err = power_domain_get(dev, &pcie->pwrdom);
1144 if (err) {
1145 debug("power_domain_get() failed: %d\n", err);
1146 return err;
1147 }
1148#endif
1149
Simon Glass46fcfc12015-11-19 20:27:02 -07001150 err = tegra_pcie_power_on(pcie);
1151 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001152 pr_err("failed to power on");
Simon Glass46fcfc12015-11-19 20:27:02 -07001153 return err;
1154 }
Thierry Reding412c7582014-12-09 22:25:12 -07001155
Simon Glass46fcfc12015-11-19 20:27:02 -07001156 err = tegra_pcie_enable_controller(pcie);
1157 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001158 pr_err("failed to enable controller");
Simon Glass46fcfc12015-11-19 20:27:02 -07001159 return err;
1160 }
Thierry Reding412c7582014-12-09 22:25:12 -07001161
Simon Glass46fcfc12015-11-19 20:27:02 -07001162 err = tegra_pcie_setup_translations(dev);
1163 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001164 pr_err("failed to decode ranges");
Simon Glass46fcfc12015-11-19 20:27:02 -07001165 return err;
1166 }
Thierry Reding412c7582014-12-09 22:25:12 -07001167
Simon Glass46fcfc12015-11-19 20:27:02 -07001168 err = tegra_pcie_enable(pcie);
1169 if (err < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001170 pr_err("failed to enable PCIe");
Simon Glass46fcfc12015-11-19 20:27:02 -07001171 return err;
Thierry Reding412c7582014-12-09 22:25:12 -07001172 }
1173
1174 return 0;
1175}
1176
Simon Glass46fcfc12015-11-19 20:27:02 -07001177static const struct dm_pci_ops pci_tegra_ops = {
1178 .read_config = pci_tegra_read_config,
1179 .write_config = pci_tegra_write_config,
1180};
Thierry Reding412c7582014-12-09 22:25:12 -07001181
Simon Glass46fcfc12015-11-19 20:27:02 -07001182static const struct udevice_id pci_tegra_ids[] = {
1183 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1184 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1185 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1186 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
Stephen Warren86f6a942016-08-05 16:10:34 -06001187 { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
Simon Glass46fcfc12015-11-19 20:27:02 -07001188 { }
1189};
Thierry Reding412c7582014-12-09 22:25:12 -07001190
Simon Glass46fcfc12015-11-19 20:27:02 -07001191U_BOOT_DRIVER(pci_tegra) = {
1192 .name = "pci_tegra",
1193 .id = UCLASS_PCI,
1194 .of_match = pci_tegra_ids,
1195 .ops = &pci_tegra_ops,
Simon Glassaad29ae2020-12-03 16:55:21 -07001196 .of_to_plat = pci_tegra_of_to_plat,
Simon Glass46fcfc12015-11-19 20:27:02 -07001197 .probe = pci_tegra_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001198 .priv_auto = sizeof(struct tegra_pcie),
Simon Glass46fcfc12015-11-19 20:27:02 -07001199};