Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the WB45N CPU Module. |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_H__ |
| 7 | #define __CONFIG_H__ |
| 8 | |
| 9 | #include <asm/hardware.h> |
| 10 | |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 11 | /* ARM asynchronous clock */ |
| 12 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
| 13 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ |
| 14 | |
| 15 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 16 | #define CONFIG_SETUP_MEMORY_TAGS |
| 17 | #define CONFIG_INITRD_TAG |
| 18 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 19 | |
| 20 | /* general purpose I/O */ |
| 21 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ |
| 22 | #define CONFIG_AT91_GPIO |
| 23 | |
| 24 | /* serial console */ |
| 25 | #define CONFIG_ATMEL_USART |
| 26 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 27 | #define CONFIG_USART_ID ATMEL_ID_SYS |
| 28 | |
| 29 | /* |
| 30 | * BOOTP options |
| 31 | */ |
| 32 | #define CONFIG_BOOTP_BOOTFILESIZE |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 33 | |
| 34 | /* SDRAM */ |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 35 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 36 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ |
| 37 | |
| 38 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 39 | (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) |
| 40 | |
| 41 | /* NAND flash */ |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 42 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 43 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 44 | /* our ALE is AD21 */ |
| 45 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 46 | /* our CLE is AD22 */ |
| 47 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 48 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 |
| 49 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 |
| 50 | |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 51 | #define CONFIG_RBTREE |
| 52 | #define CONFIG_LZO |
| 53 | |
| 54 | /* Ethernet */ |
| 55 | #define CONFIG_MACB |
| 56 | #define CONFIG_RMII |
| 57 | #define CONFIG_NET_RETRY_COUNT 20 |
| 58 | #define CONFIG_MACB_SEARCH_PHY |
| 59 | #define CONFIG_ETHADDR C0:EE:40:00:00:00 |
| 60 | #define CONFIG_ENV_OVERWRITE 1 |
| 61 | |
| 62 | /* System */ |
| 63 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 64 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 65 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
| 66 | |
| 67 | #ifdef CONFIG_SYS_USE_NANDFLASH |
| 68 | /* bootstrap + u-boot + env + linux in nandflash */ |
| 69 | #define CONFIG_ENV_OFFSET 0xa0000 |
| 70 | #define CONFIG_ENV_OFFSET_REDUND 0xc0000 |
| 71 | #define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */ |
| 72 | |
| 73 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ |
| 74 | "run _mtd; bootm" |
| 75 | |
| 76 | #define MTDIDS_DEFAULT "nand0=atmel_nand" |
| 77 | #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ |
| 78 | "128K(at91bs)," \ |
| 79 | "512K(u-boot)," \ |
| 80 | "128K(u-boot-env)," \ |
| 81 | "128K(redund-env)," \ |
| 82 | "2560K(kernel-a)," \ |
| 83 | "2560K(kernel-b)," \ |
| 84 | "38912K(rootfs-a)," \ |
| 85 | "38912K(rootfs-b)," \ |
| 86 | "46208K(user)," \ |
| 87 | "512K(logs)" |
| 88 | |
| 89 | #else |
| 90 | #error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' |
| 91 | #endif |
| 92 | |
| 93 | #define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \ |
| 94 | "rw noinitrd mem=64M " \ |
| 95 | "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" |
| 96 | |
| 97 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 98 | "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ |
| 99 | "autoload=no\0" \ |
| 100 | "autostart=no\0" \ |
| 101 | "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ |
| 102 | "\0" |
| 103 | |
| 104 | #define CONFIG_SYS_CBSIZE 256 |
| 105 | #define CONFIG_SYS_MAXARGS 16 |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 106 | |
| 107 | /* |
| 108 | * Size of malloc() pool |
| 109 | */ |
| 110 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) |
| 111 | |
| 112 | /* SPL */ |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 113 | #define CONFIG_SPL_MAX_SIZE 0x6000 |
| 114 | #define CONFIG_SPL_STACK 0x308000 |
| 115 | |
| 116 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 117 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 118 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 119 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 120 | |
| 121 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 122 | |
| 123 | #define CONFIG_SYS_MASTER_CLOCK 132096000 |
| 124 | #define CONFIG_SYS_AT91_PLLA 0x20c73f03 |
| 125 | #define CONFIG_SYS_MCKR 0x1301 |
| 126 | #define CONFIG_SYS_MCKR_CSS 0x1302 |
| 127 | |
| 128 | #define CONFIG_SPL_NAND_DRIVERS |
| 129 | #define CONFIG_SPL_NAND_BASE |
| 130 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 |
| 131 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 132 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 |
| 133 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 134 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 135 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 |
| 136 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 |
Ben Whitten | 7b8f9af | 2017-11-23 13:47:47 +0000 | [diff] [blame] | 137 | |
| 138 | #endif /* __CONFIG_H__ */ |