Blame - arch/arm/dts/imx7ulp-pinfunc.h - filogic/uboot

Peng Fan

adaf8be

2017-02-22 16:21:54 +0800

[diff] [blame]

/*

*

* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License version 2 as

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* published by the Free Software Foundation.

*

*/

#ifndef __DTS_ULP1_PINFUNC_H

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#define __DTS_ULP1_PINFUNC_H

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/*

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* The pin function ID is a tuple of

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* <mux_conf_reg mux2_reg mux_mode mux2_val>

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*

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* !!! IMPORTANT NOTE !!!

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*

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* There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first

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* two values are defined as same value. Extra non-zero mux2_reg value within the tuple

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* means that there's additional mux2 control register that must be configured to

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* mux2_val accordingly to fetch desired pin functionality on ULP1 device.

*

*/

#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0

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#define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0

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#define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0

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#define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2

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#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2

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#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2

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#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2

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#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2

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#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0

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#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0

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#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1

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#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0

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#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1

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#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1

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#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1

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#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0

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#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0

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#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1

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#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1

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#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1

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#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1

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#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1

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#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0

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#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0

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#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0

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#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0

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#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1

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#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1

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#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1

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#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0

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#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0

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#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1

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#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1

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#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1

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#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1

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#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1

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#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0

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#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0

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#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1

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#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0

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#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1

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#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1

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#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1

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#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0

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#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0

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#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1

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#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1

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#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1

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#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1

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#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1

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#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0

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#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0

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#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1

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#define ULP1_PAD_PTA7__LPUART1_RX 0x001c 0xd208 0x4 0x1

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#define ULP1_PAD_PTA7__TPM1_CH1 0x001c 0xd154 0x6 0x1

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#define ULP1_PAD_PTA7__I2S0_TXD0 0x001c 0x0000 0x7 0x0

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#define ULP1_PAD_PTA8__ADC1_CH7A 0x0020 0x0000 0x0 0x0

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#define ULP1_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0

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#define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1

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#define ULP1_PAD_PTA8__LPUART2_CTS_B 0x0020 0xd210 0x4 0x1

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#define ULP1_PAD_PTA8__LPI2C2_SCL 0x0020 0xd194 0x5 0x1

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#define ULP1_PAD_PTA8__TPM1_CLKIN 0x0020 0xd1ac 0x6 0x1

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#define ULP1_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0

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#define ULP1_PAD_PTA9__ADC1_CH7B 0x0024 0x0000 0x0 0x0

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#define ULP1_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0

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#define ULP1_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0

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#define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1

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#define ULP1_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0

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#define ULP1_PAD_PTA9__LPI2C2_SDA 0x0024 0xd198 0x5 0x1

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#define ULP1_PAD_PTA9__TPM1_CH0 0x0024 0xd150 0x6 0x1

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#define ULP1_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0

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#define ULP1_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0

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#define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1

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#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1

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#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1

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#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1

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#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1

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#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0

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#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0

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#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1

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#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1

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#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2

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#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0

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#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0

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#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1

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#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1

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#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1

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#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1

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#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2

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#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0

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#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0

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#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0

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#define ULP1_PAD_PTA13_LLWU0_P2__LLWU0_P2 0x0034 0x0000 0xd 0x0

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#define ULP1_PAD_PTA13_LLWU0_P2__LPSPI1_SOUT 0x0034 0xd134 0x3 0x2

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#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0

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#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2

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#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1

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#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2

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#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0

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#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0

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#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0

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#define ULP1_PAD_PTA14_LLWU0_P3__LPSPI1_SCK 0x0038 0xd12c 0x3 0x2

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#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2

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#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2

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#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1

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#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2

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#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0

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#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0

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#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1

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#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1

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#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1

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#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2

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#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0

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#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0

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#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0

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#define ULP1_PAD_PTA16__LPSPI0_PCS1 0x0040 0xd104 0x3 0x1

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#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1

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#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1

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#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1

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#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2

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#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0

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#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0

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#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0

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#define ULP1_PAD_PTA17__LPSPI0_PCS2 0x0044 0xd108 0x3 0x2

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#define ULP1_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0

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#define ULP1_PAD_PTA17__LPI2C0_SDA 0x0044 0xd180 0x5 0x2

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#define ULP1_PAD_PTA17__TPM3_CH3 0x0044 0xd16c 0x6 0x1

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#define ULP1_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0

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#define ULP1_PAD_PTA18_LLWU0_P4__CMP1_IN1A 0x0048 0x0000 0x0 0x0

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#define ULP1_PAD_PTA18_LLWU0_P4__PTA18 0x0048 0x0000 0x1 0x0

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#define ULP1_PAD_PTA18_LLWU0_P4__NMI1_B 0x0048 0x0000 0xb 0x0

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#define ULP1_PAD_PTA18_LLWU0_P4__LLWU0_P4 0x0048 0x0000 0xd 0x0

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#define ULP1_PAD_PTA18_LLWU0_P4__FXIO0_D2 0x0048 0x0000 0x2 0x0

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#define ULP1_PAD_PTA18_LLWU0_P4__LPSPI0_PCS3 0x0048 0xd10c 0x3 0x2

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#define ULP1_PAD_PTA18_LLWU0_P4__LPUART0_TX 0x0048 0xd200 0x4 0x2

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#define ULP1_PAD_PTA18_LLWU0_P4__LPI2C0_HREQ 0x0048 0xd178 0x5 0x2

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#define ULP1_PAD_PTA18_LLWU0_P4__TPM3_CH4 0x0048 0xd170 0x6 0x1

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#define ULP1_PAD_PTA18_LLWU0_P4__I2S0_TXD1 0x0048 0x0000 0x7 0x0

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#define ULP1_PAD_PTA19_LLWU0_P5__CMP1_IN1B 0x004c 0x0000 0x0 0x0

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#define ULP1_PAD_PTA19_LLWU0_P5__PTA19 0x004c 0x0000 0x1 0x0

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#define ULP1_PAD_PTA19_LLWU0_P5__LPTMR0_ALT3 0x004c 0x0000 0xb 0x0

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#define ULP1_PAD_PTA19_LLWU0_P5__LLWU0_P5 0x004c 0x0000 0xd 0x0

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#define ULP1_PAD_PTA19_LLWU0_P5__FXIO0_D3 0x004c 0x0000 0x2 0x0

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#define ULP1_PAD_PTA19_LLWU0_P5__LPUART0_RX 0x004c 0xd1fc 0x4 0x2

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#define ULP1_PAD_PTA19_LLWU0_P5__TPM3_CH5 0x004c 0xd174 0x6 0x1

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#define ULP1_PAD_PTA19_LLWU0_P5__I2S1_RX_BCLK 0x004c 0xd1cc 0x7 0x1

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#define ULP1_PAD_PTA20__ADC0_CH7A 0x0050 0x0000 0x0 0x0

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#define ULP1_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0

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#define ULP1_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0

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#define ULP1_PAD_PTA20__LPSPI0_SIN 0x0050 0xd114 0x3 0x2

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#define ULP1_PAD_PTA20__LPUART1_CTS_B 0x0050 0xd204 0x4 0x2

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#define ULP1_PAD_PTA20__LPI2C1_SCL 0x0050 0xd188 0x5 0x2

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#define ULP1_PAD_PTA20__TPM0_CLKIN 0x0050 0xd1a8 0x6 0x1

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#define ULP1_PAD_PTA20__I2S1_RX_FS 0x0050 0xd1d0 0x7 0x1

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#define ULP1_PAD_PTA21__ADC0_CH7B 0x0054 0x0000 0x0 0x0

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#define ULP1_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0

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#define ULP1_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0

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#define ULP1_PAD_PTA21__LPSPI0_SOUT 0x0054 0xd118 0x3 0x2

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#define ULP1_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0

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#define ULP1_PAD_PTA21__LPI2C1_SDA 0x0054 0xd18c 0x5 0x2

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#define ULP1_PAD_PTA21__TPM0_CH0 0x0054 0xd138 0x6 0x2

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#define ULP1_PAD_PTA21__I2S1_RXD0 0x0054 0xd1e4 0x7 0x1

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#define ULP1_PAD_PTA22__ADC0_CH6A 0x0058 0x0000 0x0 0x0

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#define ULP1_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0

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#define ULP1_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0

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#define ULP1_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0

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#define ULP1_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0

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#define ULP1_PAD_PTA22__LPSPI0_SCK 0x0058 0xd110 0x3 0x2

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#define ULP1_PAD_PTA22__LPUART1_TX 0x0058 0xd20c 0x4 0x2

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#define ULP1_PAD_PTA22__LPI2C1_HREQ 0x0058 0xd184 0x5 0x2

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#define ULP1_PAD_PTA22__TPM0_CH1 0x0058 0xd13c 0x6 0x2

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#define ULP1_PAD_PTA22__I2S1_RXD1 0x0058 0xd1e8 0x7 0x1

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#define ULP1_PAD_PTA23_LLWU0_P6__ADC0_CH6B 0x005c 0x0000 0x0 0x0

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#define ULP1_PAD_PTA23_LLWU0_P6__PTA23 0x005c 0x0000 0x1 0x0

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#define ULP1_PAD_PTA23_LLWU0_P6__LLWU0_P6 0x005c 0x0000 0xd 0x0

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#define ULP1_PAD_PTA23_LLWU0_P6__FXIO0_D7 0x005c 0x0000 0x2 0x0

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#define ULP1_PAD_PTA23_LLWU0_P6__LPSPI0_PCS0 0x005c 0xd100 0x3 0x2

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#define ULP1_PAD_PTA23_LLWU0_P6__LPUART1_RX 0x005c 0xd208 0x4 0x2

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#define ULP1_PAD_PTA23_LLWU0_P6__TPM0_CH2 0x005c 0xd140 0x6 0x2

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#define ULP1_PAD_PTA23_LLWU0_P6__I2S1_MCLK 0x005c 0xd1c8 0x7 0x1

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#define ULP1_PAD_PTA24__ADC0_CH5A 0x0060 0x0000 0x0 0x0

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#define ULP1_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0

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#define ULP1_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0

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#define ULP1_PAD_PTA24__LPSPI1_PCS1 0x0060 0xd120 0x3 0x2

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#define ULP1_PAD_PTA24__LPUART2_CTS_B 0x0060 0xd210 0x4 0x2

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#define ULP1_PAD_PTA24__LPI2C2_SCL 0x0060 0xd194 0x5 0x2

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#define ULP1_PAD_PTA24__TPM0_CH3 0x0060 0xd144 0x6 0x2

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#define ULP1_PAD_PTA24__I2S1_TX_BCLK 0x0060 0xd1d4 0x7 0x1

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#define ULP1_PAD_PTA25__ADC0_CH5B 0x0064 0x0000 0x0 0x0

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#define ULP1_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0

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#define ULP1_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0

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#define ULP1_PAD_PTA25__LPSPI1_PCS2 0x0064 0xd124 0x3 0x2

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#define ULP1_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0

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#define ULP1_PAD_PTA25__LPI2C2_SDA 0x0064 0xd198 0x5 0x2

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#define ULP1_PAD_PTA25__TPM0_CH4 0x0064 0xd148 0x6 0x2

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#define ULP1_PAD_PTA25__I2S1_TX_FS 0x0064 0xd1d8 0x7 0x1

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#define ULP1_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0

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#define ULP1_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0

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#define ULP1_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0

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#define ULP1_PAD_PTA26__LPSPI1_PCS3 0x0068 0xd128 0x3 0x2

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#define ULP1_PAD_PTA26__LPUART2_TX 0x0068 0xd218 0x4 0x2

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#define ULP1_PAD_PTA26__LPI2C2_HREQ 0x0068 0xd190 0x5 0x2

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#define ULP1_PAD_PTA26__TPM0_CH5 0x0068 0xd14c 0x6 0x2

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#define ULP1_PAD_PTA26__I2S1_RXD2 0x0068 0xd1ec 0x7 0x1

230

#define ULP1_PAD_PTA27__PTA27 0x006c 0x0000 0x1 0x0

231

#define ULP1_PAD_PTA27__JTAG_TDO 0x006c 0x0000 0xa 0x0

232

#define ULP1_PAD_PTA27__FXIO0_D11 0x006c 0x0000 0x2 0x0

233

#define ULP1_PAD_PTA27__LPUART2_RX 0x006c 0xd214 0x4 0x2

234

#define ULP1_PAD_PTA27__TPM1_CH1 0x006c 0xd154 0x6 0x2

235

#define ULP1_PAD_PTA27__I2S1_RXD3 0x006c 0xd1f0 0x7 0x1

236

#define ULP1_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0

237

#define ULP1_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0

238

#define ULP1_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0

239

#define ULP1_PAD_PTA28__LPSPI1_SIN 0x0070 0xd130 0x3 0x2

240

#define ULP1_PAD_PTA28__LPUART3_CTS_B 0x0070 0xd21c 0x4 0x2

241

#define ULP1_PAD_PTA28__LPI2C3_SCL 0x0070 0xd1a0 0x5 0x2

242

#define ULP1_PAD_PTA28__TPM1_CLKIN 0x0070 0xd1ac 0x6 0x2

243

#define ULP1_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0

244

#define ULP1_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0

245

#define ULP1_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0

246

#define ULP1_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0

247

#define ULP1_PAD_PTA29__LPSPI1_SOUT 0x0074 0xd134 0x3 0x1

248

#define ULP1_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0

249

#define ULP1_PAD_PTA29__LPI2C3_SDA 0x0074 0xd1a4 0x5 0x1

250

#define ULP1_PAD_PTA29__TPM1_CH0 0x0074 0xd150 0x6 0x2

251

#define ULP1_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0

252

#define ULP1_PAD_PTA30__ADC0_CH4A 0x0078 0x0000 0x0 0x0

253

#define ULP1_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0

254

#define ULP1_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0

255

#define ULP1_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0

256

#define ULP1_PAD_PTA30__LPSPI1_SCK 0x0078 0xd12c 0x3 0x1

257

#define ULP1_PAD_PTA30__LPUART3_TX 0x0078 0xd224 0x4 0x1

258

#define ULP1_PAD_PTA30__LPI2C3_HREQ 0x0078 0xd19c 0x5 0x1

259

#define ULP1_PAD_PTA30__TPM2_CLKIN 0x0078 0xd1f4 0x6 0x2

260

#define ULP1_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0

261

#define ULP1_PAD_PTA31_LLWU0_P7__ADC0_CH4B 0x007c 0x0000 0x0 0x0

262

#define ULP1_PAD_PTA31_LLWU0_P7__PTA31 0x007c 0x0000 0x1 0x0

263

#define ULP1_PAD_PTA31_LLWU0_P7__LPTMR0_ALT1 0x007c 0x0000 0xb 0x0

264

#define ULP1_PAD_PTA31_LLWU0_P7__EWM_IN 0x007c 0xd228 0xc 0x1

265

#define ULP1_PAD_PTA31_LLWU0_P7__LLWU0_P7 0x007c 0x0000 0xd 0x0

266

#define ULP1_PAD_PTA31_LLWU0_P7__FXIO0_D15 0x007c 0x0000 0x2 0x0

267

#define ULP1_PAD_PTA31_LLWU0_P7__LPSPI1_PCS0 0x007c 0xd11c 0x3 0x2

268

#define ULP1_PAD_PTA31_LLWU0_P7__LPUART3_RX 0x007c 0xd220 0x4 0x2

269

#define ULP1_PAD_PTA31_LLWU0_P7__TPM2_CH0 0x007c 0xd158 0x6 0x2

270

#define ULP1_PAD_PTA31_LLWU0_P7__I2S1_TXD1 0x007c 0x0000 0x7 0x0

271

#define ULP1_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0

272

#define ULP1_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0

273

#define ULP1_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0

274

#define ULP1_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0

275

#define ULP1_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0

276

#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3

277

#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3

278

#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2

279

#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0

280

#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0

281

#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0

282

#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0

283

#define ULP1_PAD_PTB1_LLWU0_P8__EWM_IN 0x0084 0xd228 0xc 0x2

284

#define ULP1_PAD_PTB1_LLWU0_P8__LLWU0_P8 0x0084 0x0000 0xd 0x0

285

#define ULP1_PAD_PTB1_LLWU0_P8__FXIO0_D17 0x0084 0x0000 0x2 0x0

286

#define ULP1_PAD_PTB1_LLWU0_P8__LPSPI0_SOUT 0x0084 0xd118 0x3 0x3

287

#define ULP1_PAD_PTB1_LLWU0_P8__LPUART0_RX 0x0084 0xd1fc 0x4 0x3

288

#define ULP1_PAD_PTB1_LLWU0_P8__TPM3_CLKIN 0x0084 0xd1b0 0x6 0x3

289

#define ULP1_PAD_PTB1_LLWU0_P8__I2S1_TX_BCLK 0x0084 0xd1d4 0x7 0x2

290

#define ULP1_PAD_PTB2__ADC0_CH1A 0x0088 0x0000 0x0 0x0

291

#define ULP1_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0

292

#define ULP1_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0

293

#define ULP1_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0

294

#define ULP1_PAD_PTB2__LPSPI0_SCK 0x0088 0xd110 0x3 0x3

295

#define ULP1_PAD_PTB2__LPUART1_TX 0x0088 0xd20c 0x4 0x3

296

#define ULP1_PAD_PTB2__TPM3_CH0 0x0088 0xd160 0x6 0x2

297

#define ULP1_PAD_PTB2__I2S1_TX_FS 0x0088 0xd1d8 0x7 0x2

298

#define ULP1_PAD_PTB3_LLWU0_P9__ADC0_CH1B 0x008c 0x0000 0x0 0x0

299

#define ULP1_PAD_PTB3_LLWU0_P9__PTB3 0x008c 0x0000 0x1 0x0

300

#define ULP1_PAD_PTB3_LLWU0_P9__TRACE_D0 0x008c 0x0000 0xa 0x0

301

#define ULP1_PAD_PTB3_LLWU0_P9__LPTMR1_ALT2 0x008c 0x0000 0xb 0x0

302

#define ULP1_PAD_PTB3_LLWU0_P9__LLWU0_P9 0x008c 0x0000 0xd 0x0

303

#define ULP1_PAD_PTB3_LLWU0_P9__FXIO0_D19 0x008c 0x0000 0x2 0x0

304

#define ULP1_PAD_PTB3_LLWU0_P9__LPSPI0_PCS0 0x008c 0xd100 0x3 0x3

305

#define ULP1_PAD_PTB3_LLWU0_P9__LPUART1_RX 0x008c 0xd208 0x4 0x3

306

#define ULP1_PAD_PTB3_LLWU0_P9__TPM3_CH1 0x008c 0xd164 0x6 0x2

307

#define ULP1_PAD_PTB3_LLWU0_P9__I2S1_TXD0 0x008c 0x0000 0x7 0x0

308

#define ULP1_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0

309

#define ULP1_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0

310

#define ULP1_PAD_PTB4__BOOTCFG0 0x0090 0x0000 0xd 0x0

311

#define ULP1_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0

312

#define ULP1_PAD_PTB4__LPSPI0_PCS1 0x0090 0xd104 0x3 0x3

313

#define ULP1_PAD_PTB4__LPUART2_TX 0x0090 0xd218 0x4 0x3

314

#define ULP1_PAD_PTB4__LPI2C0_HREQ 0x0090 0xd178 0x5 0x3

315

#define ULP1_PAD_PTB4__TPM3_CH2 0x0090 0xd168 0x6 0x2

316

#define ULP1_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0

317

#define ULP1_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0

318

#define ULP1_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0

319

#define ULP1_PAD_PTB5__BOOTCFG1 0x0094 0x0000 0xd 0x0

320

#define ULP1_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0

321

#define ULP1_PAD_PTB5__LPSPI0_PCS2 0x0094 0xd108 0x3 0x3

322

#define ULP1_PAD_PTB5__LPUART2_RX 0x0094 0xd214 0x4 0x3

323

#define ULP1_PAD_PTB5__LPI2C1_HREQ 0x0094 0xd184 0x5 0x3

324

#define ULP1_PAD_PTB5__TPM3_CH3 0x0094 0xd16c 0x6 0x2

325

#define ULP1_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0

326

#define ULP1_PAD_PTB6_LLWU0_P10__PTB6 0x0098 0x0000 0x1 0x0

327

#define ULP1_PAD_PTB6_LLWU0_P10__TRACE_D3 0x0098 0x0000 0xa 0x0

328

#define ULP1_PAD_PTB6_LLWU0_P10__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0

329

#define ULP1_PAD_PTB6_LLWU0_P10__LLWU0_P10 0x0098 0x0000 0xd 0x0

330

#define ULP1_PAD_PTB6_LLWU0_P10__FXIO0_D22 0x0098 0x0000 0x2 0x0

331

#define ULP1_PAD_PTB6_LLWU0_P10__LPSPI0_PCS3 0x0098 0xd10c 0x3 0x3

332

#define ULP1_PAD_PTB6_LLWU0_P10__LPUART3_TX 0x0098 0xd224 0x4 0x3

333

#define ULP1_PAD_PTB6_LLWU0_P10__LPI2C0_SCL 0x0098 0xd17c 0x5 0x3

334

#define ULP1_PAD_PTB6_LLWU0_P10__TPM3_CH4 0x0098 0xd170 0x6 0x2

335

#define ULP1_PAD_PTB6_LLWU0_P10__I2S1_TXD3 0x0098 0x0000 0x7 0x0

336

#define ULP1_PAD_PTB7_LLWU0_P11__PTB7 0x009c 0x0000 0x1 0x0

337

#define ULP1_PAD_PTB7_LLWU0_P11__CMP1_OUT 0x009c 0x0000 0xb 0x0

338

#define ULP1_PAD_PTB7_LLWU0_P11__LLWU0_P11 0x009c 0x0000 0xd 0x0

339

#define ULP1_PAD_PTB7_LLWU0_P11__FXIO0_D23 0x009c 0x0000 0x2 0x0

340

#define ULP1_PAD_PTB7_LLWU0_P11__LPSPI1_SIN 0x009c 0xd130 0x3 0x3

341

#define ULP1_PAD_PTB7_LLWU0_P11__LPUART3_RX 0x009c 0xd220 0x4 0x3

342

#define ULP1_PAD_PTB7_LLWU0_P11__LPI2C0_SDA 0x009c 0xd180 0x5 0x3

343

#define ULP1_PAD_PTB7_LLWU0_P11__TPM3_CH5 0x009c 0xd174 0x6 0x2

344

#define ULP1_PAD_PTB7_LLWU0_P11__I2S1_MCLK 0x009c 0xd1c8 0x7 0x2

345

#define ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x009c 0x0000 0x8 0x0

346

#define ULP1_PAD_PTB8__CMP0_IN0A 0x00a0 0x0000 0x0 0x0

347

#define ULP1_PAD_PTB8__PTB8 0x00a0 0x0000 0x1 0x0

348

#define ULP1_PAD_PTB8__RTC_CLKOUT 0x00a0 0x0000 0xb 0x0

349

#define ULP1_PAD_PTB8__FXIO0_D24 0x00a0 0x0000 0x2 0x0

350

#define ULP1_PAD_PTB8__LPSPI1_SOUT 0x00a0 0xd134 0x3 0x3

351

#define ULP1_PAD_PTB8__LPI2C1_SCL 0x00a0 0xd188 0x5 0x3

352

#define ULP1_PAD_PTB8__TPM0_CLKIN 0x00a0 0xd1a8 0x6 0x3

353

#define ULP1_PAD_PTB8__I2S1_RX_BCLK 0x00a0 0xd1cc 0x7 0x2

354

#define ULP1_PAD_PTB8__QSPIA_SS0_B 0x00a0 0x0000 0x8 0x0

355

#define ULP1_PAD_PTB9_LLWU0_P12__CMP0_IN0B 0x00a4 0x0000 0x0 0x0

356

#define ULP1_PAD_PTB9_LLWU0_P12__PTB9 0x00a4 0x0000 0x1 0x0

357

#define ULP1_PAD_PTB9_LLWU0_P12__LLWU0_P12 0x00a4 0x0000 0xd 0x0

358

#define ULP1_PAD_PTB9_LLWU0_P12__FXIO0_D25 0x00a4 0x0000 0x2 0x0

359

#define ULP1_PAD_PTB9_LLWU0_P12__LPSPI1_SCK 0x00a4 0xd12c 0x3 0x3

360

#define ULP1_PAD_PTB9_LLWU0_P12__LPI2C1_SDA 0x00a4 0xd18c 0x5 0x3

361

#define ULP1_PAD_PTB9_LLWU0_P12__TPM0_CH0 0x00a4 0xd138 0x6 0x3

362

#define ULP1_PAD_PTB9_LLWU0_P12__I2S1_RX_FS 0x00a4 0xd1d0 0x7 0x2

363

#define ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x00a4 0x0000 0x8 0x0

364

#define ULP1_PAD_PTB10__CMP0_IN1A 0x00a8 0x0000 0x0 0x0

365

#define ULP1_PAD_PTB10__PTB10 0x00a8 0x0000 0x1 0x0

366

#define ULP1_PAD_PTB10__TRACE_D4 0x00a8 0x0000 0xa 0x0

367

#define ULP1_PAD_PTB10__FXIO0_D26 0x00a8 0x0000 0x2 0x0

368

#define ULP1_PAD_PTB10__LPSPI1_PCS0 0x00a8 0xd11c 0x3 0x3

369

#define ULP1_PAD_PTB10__LPI2C2_SCL 0x00a8 0xd194 0x5 0x3

370

#define ULP1_PAD_PTB10__TPM0_CH1 0x00a8 0xd13c 0x6 0x3

371

#define ULP1_PAD_PTB10__I2S1_RXD0 0x00a8 0xd1e4 0x7 0x2

372

#define ULP1_PAD_PTB10__QSPIA_DATA7 0x00a8 0x0000 0x8 0x0

373

#define ULP1_PAD_PTB11__CMP0_IN1B 0x00ac 0x0000 0x0 0x0

374

#define ULP1_PAD_PTB11__PTB11 0x00ac 0x0000 0x1 0x0

375

#define ULP1_PAD_PTB11__TRACE_D5 0x00ac 0x0000 0xa 0x0

376

#define ULP1_PAD_PTB11__FXIO0_D27 0x00ac 0x0000 0x2 0x0

377

#define ULP1_PAD_PTB11__LPSPI1_PCS1 0x00ac 0xd120 0x3 0x3

378

#define ULP1_PAD_PTB11__LPI2C2_SDA 0x00ac 0xd198 0x5 0x3

379

#define ULP1_PAD_PTB11__TPM1_CLKIN 0x00ac 0xd1ac 0x6 0x3

380

#define ULP1_PAD_PTB11__I2S1_RXD1 0x00ac 0xd1e8 0x7 0x2

381

#define ULP1_PAD_PTB11__QSPIA_DATA6 0x00ac 0x0000 0x8 0x0

382

#define ULP1_PAD_PTB12__ADC1_CH0A 0x00b0 0x0000 0x0 0x0

383

#define ULP1_PAD_PTB12__PTB12 0x00b0 0x0000 0x1 0x0

384

#define ULP1_PAD_PTB12__TRACE_D6 0x00b0 0x0000 0xa 0x0

385

#define ULP1_PAD_PTB12__FXIO0_D28 0x00b0 0x0000 0x2 0x0

386

#define ULP1_PAD_PTB12__LPSPI1_PCS2 0x00b0 0xd124 0x3 0x3

387

#define ULP1_PAD_PTB12__LPI2C3_SCL 0x00b0 0xd1a0 0x5 0x3

388

#define ULP1_PAD_PTB12__TPM1_CH0 0x00b0 0xd150 0x6 0x3

389

#define ULP1_PAD_PTB12__I2S1_RXD2 0x00b0 0xd1ec 0x7 0x2

390

#define ULP1_PAD_PTB12__QSPIA_DATA5 0x00b0 0x0000 0x8 0x0

391

#define ULP1_PAD_PTB13__ADC1_CH0B 0x00b4 0x0000 0x0 0x0

392

#define ULP1_PAD_PTB13__PTB13 0x00b4 0x0000 0x1 0x0

393

#define ULP1_PAD_PTB13__TRACE_D7 0x00b4 0x0000 0xa 0x0

394

#define ULP1_PAD_PTB13__FXIO0_D29 0x00b4 0x0000 0x2 0x0

395

#define ULP1_PAD_PTB13__LPSPI1_PCS3 0x00b4 0xd128 0x3 0x3

396

#define ULP1_PAD_PTB13__LPI2C3_SDA 0x00b4 0xd1a4 0x5 0x3

397

#define ULP1_PAD_PTB13__TPM1_CH1 0x00b4 0xd154 0x6 0x3

398

#define ULP1_PAD_PTB13__I2S1_RXD3 0x00b4 0xd1f0 0x7 0x2

399

#define ULP1_PAD_PTB13__QSPIA_DATA4 0x00b4 0x0000 0x8 0x0

400

#define ULP1_PAD_PTB14_LLWU0_P13__ADC1_CH1A 0x00b8 0x0000 0x0 0x0

401

#define ULP1_PAD_PTB14_LLWU0_P13__PTB14 0x00b8 0x0000 0x1 0x0

402

#define ULP1_PAD_PTB14_LLWU0_P13__LLWU0_P13 0x00b8 0x0000 0xd 0x0

403

#define ULP1_PAD_PTB14_LLWU0_P13__FXIO0_D30 0x00b8 0x0000 0x2 0x0

404

#define ULP1_PAD_PTB14_LLWU0_P13__LPI2C2_HREQ 0x00b8 0xd190 0x5 0x3

405

#define ULP1_PAD_PTB14_LLWU0_P13__TPM2_CLKIN 0x00b8 0xd1f4 0x6 0x3

406

#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SS0_B 0x00b8 0x0000 0x8 0x0

407

#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SCLK_B 0x00b8 0x0000 0x9 0x0

408

#define ULP1_PAD_PTB15__ADC1_CH1B 0x00bc 0x0000 0x0 0x0

409

#define ULP1_PAD_PTB15__PTB15 0x00bc 0x0000 0x1 0x0

410

#define ULP1_PAD_PTB15__FXIO0_D31 0x00bc 0x0000 0x2 0x0

411

#define ULP1_PAD_PTB15__LPI2C3_HREQ 0x00bc 0xd19c 0x5 0x3

412

#define ULP1_PAD_PTB15__TPM2_CH0 0x00bc 0xd158 0x6 0x3

413

#define ULP1_PAD_PTB15__QSPIA_SCLK 0x00bc 0x0000 0x8 0x0

414

#define ULP1_PAD_PTB16_LLWU0_P14__ADC0_CH2A 0x00c0 0x0000 0x0 0x0

415

#define ULP1_PAD_PTB16_LLWU0_P14__PTB16 0x00c0 0x0000 0x1 0x0

416

#define ULP1_PAD_PTB16_LLWU0_P14__LLWU0_P14 0x00c0 0x0000 0xd 0x0

417

#define ULP1_PAD_PTB16_LLWU0_P14__TPM2_CH1 0x00c0 0xd15c 0x6 0x3

418

#define ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x00c0 0x0000 0x8 0x0

419

#define ULP1_PAD_PTB17__ADC0_CH2B 0x00c4 0x0000 0x0 0x0

420

#define ULP1_PAD_PTB17__PTB17 0x00c4 0x0000 0x1 0x0

421

#define ULP1_PAD_PTB17__TPM3_CLKIN 0x00c4 0xd1b0 0x6 0x2

422

#define ULP1_PAD_PTB17__QSPIA_DATA2 0x00c4 0x0000 0x8 0x0

423

#define ULP1_PAD_PTB18__ADC0_CH3A 0x00c8 0x0000 0x0 0x0

424

#define ULP1_PAD_PTB18__PTB18 0x00c8 0x0000 0x1 0x0

425

#define ULP1_PAD_PTB18__TPM3_CH0 0x00c8 0xd160 0x6 0x3

426

#define ULP1_PAD_PTB18__QSPIA_DATA1 0x00c8 0x0000 0x8 0x0

427

#define ULP1_PAD_PTB19_LLWU0_P15__ADC0_CH3B 0x00cc 0x0000 0x0 0x0

428

#define ULP1_PAD_PTB19_LLWU0_P15__PTB19 0x00cc 0x0000 0x1 0x0

429

#define ULP1_PAD_PTB19_LLWU0_P15__USB0_ID 0x00cc 0x0000 0xa 0x0

430

#define ULP1_PAD_PTB19_LLWU0_P15__LLWU0_P15 0x00cc 0x0000 0xd 0x0

431

#define ULP1_PAD_PTB19_LLWU0_P15__TPM3_CH1 0x00cc 0xd164 0x6 0x3

432

#define ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x00cc 0x0000 0x8 0x0

433

#define ULP1_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0

434

#define ULP1_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0

435

#define ULP1_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1

436

#define ULP1_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1

437

#define ULP1_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1

438

#define ULP1_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0

439

#define ULP1_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0

440

#define ULP1_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0

441

#define ULP1_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0

442

#define ULP1_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1

443

#define ULP1_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1

444

#define ULP1_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0

445

#define ULP1_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0

446

#define ULP1_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0

447

#define ULP1_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1

448

#define ULP1_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1

449

#define ULP1_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1

450

#define ULP1_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0

451

#define ULP1_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0

452

#define ULP1_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0

453

#define ULP1_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1

454

#define ULP1_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1

455

#define ULP1_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0

456

#define ULP1_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0

457

#define ULP1_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0

458

#define ULP1_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1

459

#define ULP1_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1

460

#define ULP1_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1

461

#define ULP1_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1

462

#define ULP1_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1

463

#define ULP1_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0

464

#define ULP1_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0

465

#define ULP1_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0

466

#define ULP1_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1

467

#define ULP1_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1

468

#define ULP1_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0

469

#define ULP1_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1

470

#define ULP1_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1

471

#define ULP1_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0

472

#define ULP1_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0

473

#define ULP1_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0

474

#define ULP1_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1

475

#define ULP1_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1

476

#define ULP1_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1

477

#define ULP1_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1

478

#define ULP1_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1

479

#define ULP1_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0

480

#define ULP1_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0

481

#define ULP1_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0

482

#define ULP1_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1

483

#define ULP1_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1

484

#define ULP1_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1

485

#define ULP1_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0

486

#define ULP1_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0

487

#define ULP1_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0

488

#define ULP1_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1

489

#define ULP1_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1

490

#define ULP1_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1

491

#define ULP1_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1

492

#define ULP1_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1

493

#define ULP1_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0

494

#define ULP1_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0

495

#define ULP1_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0

496

#define ULP1_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1

497

#define ULP1_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1

498

#define ULP1_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0

499

#define ULP1_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1

500

#define ULP1_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1

501

#define ULP1_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0

502

#define ULP1_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0

503

#define ULP1_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0

504

#define ULP1_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1

505

#define ULP1_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1

506

#define ULP1_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1

507

#define ULP1_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1

508

#define ULP1_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1

509

#define ULP1_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0

510

#define ULP1_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0

511

#define ULP1_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0

512

#define ULP1_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1

513

#define ULP1_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1

514

#define ULP1_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1

515

#define ULP1_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1

516

#define ULP1_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0

517

#define ULP1_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0

518

#define ULP1_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0

519

#define ULP1_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1

520

#define ULP1_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1

521

#define ULP1_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1

522

#define ULP1_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1

523

#define ULP1_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1

524

#define ULP1_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0

525

#define ULP1_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0

526

#define ULP1_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0

527

#define ULP1_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1

528

#define ULP1_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1

529

#define ULP1_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0

530

#define ULP1_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1

531

#define ULP1_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1

532

#define ULP1_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0

533

#define ULP1_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0

534

#define ULP1_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0

535

#define ULP1_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1

536

#define ULP1_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1

537

#define ULP1_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1

538

#define ULP1_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1

539

#define ULP1_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1

540

#define ULP1_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0

541

#define ULP1_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0

542

#define ULP1_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0

543

#define ULP1_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1

544

#define ULP1_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1

545

#define ULP1_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1

546

#define ULP1_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0

547

#define ULP1_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0

548

#define ULP1_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0

549

#define ULP1_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1

550

#define ULP1_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1

551

#define ULP1_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1

552

#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0

553

#define ULP1_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0

554

#define ULP1_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1

555

#define ULP1_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1

556

#define ULP1_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1

557

#define ULP1_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0

558

#define ULP1_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0

559

#define ULP1_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1

560

#define ULP1_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1

561

#define ULP1_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1

562

#define ULP1_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0

563

#define ULP1_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0

564

#define ULP1_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1

565

#define ULP1_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1

566

#define ULP1_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1

567

#define ULP1_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0

568

#define ULP1_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0

569

#define ULP1_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0

570

#define ULP1_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0

571

#define ULP1_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0

572

#define ULP1_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0

573

#define ULP1_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0

574

#define ULP1_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0

575

#define ULP1_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0

576

#define ULP1_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0

577

#define ULP1_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0

578

#define ULP1_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0

579

#define ULP1_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0

580

#define ULP1_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0

581

#define ULP1_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0

582

#define ULP1_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0

583

#define ULP1_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0

584

#define ULP1_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0

585

#define ULP1_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2

586

#define ULP1_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0

587

#define ULP1_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0

588

#define ULP1_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2

589

#define ULP1_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0

590

#define ULP1_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0

591

#define ULP1_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2

592

#define ULP1_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0

593

#define ULP1_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0

594

#define ULP1_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2

595

#define ULP1_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0

596

#define ULP1_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0

597

#define ULP1_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0

598

#define ULP1_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2

599

#define ULP1_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2

600

#define ULP1_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2

601

#define ULP1_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0

602

#define ULP1_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0

603

#define ULP1_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0

604

#define ULP1_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0

605

#define ULP1_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2

606

#define ULP1_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0

607

#define ULP1_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2

608

#define ULP1_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0

609

#define ULP1_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0

610

#define ULP1_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0

611

#define ULP1_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0

612

#define ULP1_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2

613

#define ULP1_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2

614

#define ULP1_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2

615

#define ULP1_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0

616

#define ULP1_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0

617

#define ULP1_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0

618

#define ULP1_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2

619

#define ULP1_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2

620

#define ULP1_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0

621

#define ULP1_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0

622

#define ULP1_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0

623

#define ULP1_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2

624

#define ULP1_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2

625

#define ULP1_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2

626

#define ULP1_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2

627

#define ULP1_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0

628

#define ULP1_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0

629

#define ULP1_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0

630

#define ULP1_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2

631

#define ULP1_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0

632

#define ULP1_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2

633

#define ULP1_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2

634

#define ULP1_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0

635

#define ULP1_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0

636

#define ULP1_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0

637

#define ULP1_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2

638

#define ULP1_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2

639

#define ULP1_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2

640

#define ULP1_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2

641

#define ULP1_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0

642

#define ULP1_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0

643

#define ULP1_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0

644

#define ULP1_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0

645

#define ULP1_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0

646

#define ULP1_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0

647

#define ULP1_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2

648

#define ULP1_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2

649

#define ULP1_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2

650

#define ULP1_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0

651

#define ULP1_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0

652

#define ULP1_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0

653

#define ULP1_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0

654

#define ULP1_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0

655

#define ULP1_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0

656

#define ULP1_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2

657

#define ULP1_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2

658

#define ULP1_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2

659

#define ULP1_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2

660

#define ULP1_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1

661

#define ULP1_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0

662

#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0

663

#define ULP1_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0

664

#define ULP1_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0

665

#define ULP1_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0

666

#define ULP1_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0

667

#define ULP1_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2

668

#define ULP1_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0

669

#define ULP1_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2

670

#define ULP1_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2

671

#define ULP1_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1

672

#define ULP1_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0

673

#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0

674

#define ULP1_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0

675

#define ULP1_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0

676

#define ULP1_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0

677

#define ULP1_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0

678

#define ULP1_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2

679

#define ULP1_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2

680

#define ULP1_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2

681

#define ULP1_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2

682

#define ULP1_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0

683

#define ULP1_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0

684

#define ULP1_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0

685

#define ULP1_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0

686

#define ULP1_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0

687

#define ULP1_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0

688

#define ULP1_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0

689

#define ULP1_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2

690

#define ULP1_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2

691

#define ULP1_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0

692

#define ULP1_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0

693

#define ULP1_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0

694

#define ULP1_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0

695

#define ULP1_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0

696

#define ULP1_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0

697

#define ULP1_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2

698

#define ULP1_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2

699

#define ULP1_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2

700

#define ULP1_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2

701

#define ULP1_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2

702

#define ULP1_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0

703

#define ULP1_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0

704

#define ULP1_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0

705

#define ULP1_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0

706

#define ULP1_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0

707

#define ULP1_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2

708

#define ULP1_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0

709

#define ULP1_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2

710

#define ULP1_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2

711

#define ULP1_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2

712

#define ULP1_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0

713

#define ULP1_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0

714

#define ULP1_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0

715

#define ULP1_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0

716

#define ULP1_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0

717

#define ULP1_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2

718

#define ULP1_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2

719

#define ULP1_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2

720

#define ULP1_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2

721

#define ULP1_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0

722

#define ULP1_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0

723

#define ULP1_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0

724

#define ULP1_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0

725

#define ULP1_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0

726

#define ULP1_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0

727

#define ULP1_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2

728

#define ULP1_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2

729

#define ULP1_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2

730

#define ULP1_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0

731

#define ULP1_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0

732

#define ULP1_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0

733

#define ULP1_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3

734

#define ULP1_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3

735

#define ULP1_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3

736

#define ULP1_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0

737

#define ULP1_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0

738

#define ULP1_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0

739

#define ULP1_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0

740

#define ULP1_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3

741

#define ULP1_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3

742

#define ULP1_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0

743

#define ULP1_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0

744

#define ULP1_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0

745

#define ULP1_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3

746

#define ULP1_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3

747

#define ULP1_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3

748

#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0

749

#define ULP1_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0

750

#define ULP1_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0

751

#define ULP1_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3

752

#define ULP1_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3

753

#define ULP1_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0

754

#define ULP1_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0

755

#define ULP1_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0

756

#define ULP1_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2

757

#define ULP1_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3

758

#define ULP1_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3

759

#define ULP1_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3

760

#define ULP1_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2

761

#define ULP1_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0

762

#define ULP1_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0

763

#define ULP1_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0

764

#define ULP1_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2

765

#define ULP1_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3

766

#define ULP1_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0

767

#define ULP1_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3

768

#define ULP1_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2

769

#define ULP1_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0

770

#define ULP1_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0

771

#define ULP1_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0

772

#define ULP1_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2

773

#define ULP1_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3

774

#define ULP1_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3

775

#define ULP1_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3

776

#define ULP1_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2

777

#define ULP1_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0

778

#define ULP1_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0

779

#define ULP1_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0

780

#define ULP1_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2

781

#define ULP1_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3

782

#define ULP1_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3

783

#define ULP1_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0

784

#define ULP1_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0

785

#define ULP1_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0

786

#define ULP1_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0

787

#define ULP1_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2

788

#define ULP1_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3

789

#define ULP1_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3

790

#define ULP1_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3

791

#define ULP1_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3

792

#define ULP1_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0

793

#define ULP1_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0

794

#define ULP1_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0

795

#define ULP1_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0

796

#define ULP1_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2

797

#define ULP1_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3

798

#define ULP1_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0

799

#define ULP1_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3

800

#define ULP1_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3

801

#define ULP1_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0

802

#define ULP1_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0

803

#define ULP1_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0

804

#define ULP1_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0

805

#define ULP1_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2

806

#define ULP1_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3

807

#define ULP1_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3

808

#define ULP1_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3

809

#define ULP1_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3

810

#define ULP1_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0

811

#define ULP1_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0

812

#define ULP1_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0

813

#define ULP1_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0

814

#define ULP1_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2

815

#define ULP1_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3

816

#define ULP1_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3

817

#define ULP1_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3

818

#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0

819

#define ULP1_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0

820

#define ULP1_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0

821

#define ULP1_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0

822

#define ULP1_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2

823

#define ULP1_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3

824

#define ULP1_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3

825

#define ULP1_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3

826

#define ULP1_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3

827

#define ULP1_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0

828

#define ULP1_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0

829

#define ULP1_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0

830

#define ULP1_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0

831

#define ULP1_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2

832

#define ULP1_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3

833

#define ULP1_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0

834

#define ULP1_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3

835

#define ULP1_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3

836

#define ULP1_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0

837

#define ULP1_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0

838

#define ULP1_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0

839

#define ULP1_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0

840

#define ULP1_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2

841

#define ULP1_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3

842

#define ULP1_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3

843

#define ULP1_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3

844

#define ULP1_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3

845

#define ULP1_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0

846

#define ULP1_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0

847

#define ULP1_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0

848

#define ULP1_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0

849

#define ULP1_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2

850

#define ULP1_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3

851

#define ULP1_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3

852

#define ULP1_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0

853

#define ULP1_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0

854

#define ULP1_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0

855

#define ULP1_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0

856

#define ULP1_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2

857

#define ULP1_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3

858

#define ULP1_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3

859

#define ULP1_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0

860

#define ULP1_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0

861

#define ULP1_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0

862

#define ULP1_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0

863

#define ULP1_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2

864

#define ULP1_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3

865

#define ULP1_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3

866

#define ULP1_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0

867

#define ULP1_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0

868

#define ULP1_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0

869

#define ULP1_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0

870

#define ULP1_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2

871

#define ULP1_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3

872

#define ULP1_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3

873

#define ULP1_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0

874

#define ULP1_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0

875

#define ULP1_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0

876

#define ULP1_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0

877

#define ULP1_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2

878

#define ULP1_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3

879

#define ULP1_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3

880

#define ULP1_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0

881

882

#endif /* __DTS_ULP1_PINFUNC_H */