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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Stephen Warren0e012c32012-08-05 16:07:22 +00002/*
Stephen Warrend8845db2016-04-04 20:00:41 -06003 * (C) Copyright 2012-2016 Stephen Warren
Stephen Warren0e012c32012-08-05 16:07:22 +00004 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
Stephen Warrend8845db2016-04-04 20:00:41 -06009#include <linux/sizes.h>
10#include <asm/arch/timer.h>
11
Matthias Brugger2c68dee2019-11-19 16:01:03 +010012#ifndef __ASSEMBLY__
13#include <asm/arch/base.h>
14#endif
15
Stephen Warrend8845db2016-04-04 20:00:41 -060016/* Architecture, CPU, etc.*/
Stephen Warrend8845db2016-04-04 20:00:41 -060017
18/* Use SoC timer for AArch32, but architected timer for AArch64 */
19#ifndef CONFIG_ARM64
20#define CONFIG_SYS_TIMER_RATE 1000000
21#define CONFIG_SYS_TIMER_COUNTER \
22 (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
23#endif
24
Stephen Warrend8845db2016-04-04 20:00:41 -060025/* Memory layout */
Stephen Warrend8845db2016-04-04 20:00:41 -060026#define CONFIG_SYS_SDRAM_BASE 0x00000000
Stephen Warrend8845db2016-04-04 20:00:41 -060027#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
28/*
29 * The board really has 256M. However, the VC (VideoCore co-processor) shares
30 * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
31 * smaller amount of RAM is present in order to avoid stomping on the area
32 * the VC uses.
33 */
34#define CONFIG_SYS_SDRAM_SIZE SZ_128M
35#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
36 CONFIG_SYS_SDRAM_SIZE - \
37 GENERATED_GBL_DATA_SIZE)
Stephen Warrend8845db2016-04-04 20:00:41 -060038
Bonnans, Laurenta0c20302019-07-31 11:59:41 +000039#ifdef CONFIG_ARM64
40#define CONFIG_SYS_BOOTM_LEN SZ_64M
41#endif
42
Stephen Warrend8845db2016-04-04 20:00:41 -060043/* Devices */
44/* GPIO */
45#define CONFIG_BCM2835_GPIO
46/* LCD */
Stephen Warrend8845db2016-04-04 20:00:41 -060047#define CONFIG_LCD_DT_SIMPLEFB
Stephen Warrend8845db2016-04-04 20:00:41 -060048#define CONFIG_VIDEO_BCM2835
Stephen Warrend8845db2016-04-04 20:00:41 -060049
Marek Szyprowski378f5932019-12-02 12:11:18 +010050/* DFU over USB/UDC */
51#ifdef CONFIG_CMD_DFU
Marek Szyprowski378f5932019-12-02 12:11:18 +010052#ifdef CONFIG_ARM64
53#define KERNEL_FILENAME "Image"
54#else
55#define KERNEL_FILENAME "zImage"
56#endif
57
58#define ENV_DFU_SETTINGS \
59 "dfu_alt_info=u-boot.bin fat 0 1;uboot.env fat 0 1;" \
60 "config.txt fat 0 1;" \
61 KERNEL_FILENAME " fat 0 1\0"
62#else
63#define ENV_DFU_SETTINGS ""
64#endif
65
Stephen Warrend8845db2016-04-04 20:00:41 -060066/* Console configuration */
67#define CONFIG_SYS_CBSIZE 1024
Stephen Warrend8845db2016-04-04 20:00:41 -060068
69/* Environment */
Stephen Warrend8845db2016-04-04 20:00:41 -060070
71/* Shell */
Stephen Warrend8845db2016-04-04 20:00:41 -060072
Stephen Warrend8845db2016-04-04 20:00:41 -060073/* Environment */
Stephen Warrend8845db2016-04-04 20:00:41 -060074#define ENV_DEVICE_SETTINGS \
75 "stdin=serial,usbkbd\0" \
Simon Glass39254d02017-04-05 16:23:44 -060076 "stdout=serial,vidconsole\0" \
77 "stderr=serial,vidconsole\0"
Stephen Warrend8845db2016-04-04 20:00:41 -060078
Tuomas Tynkkynen8c62fc02018-04-20 13:03:48 +030079#ifdef CONFIG_ARM64
80#define FDT_HIGH "ffffffffffffffff"
81#define INITRD_HIGH "ffffffffffffffff"
82#else
83#define FDT_HIGH "ffffffff"
84#define INITRD_HIGH "ffffffff"
85#endif
86
Stephen Warrend8845db2016-04-04 20:00:41 -060087/*
88 * Memory layout for where various images get loaded by boot scripts:
89 *
90 * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
91 *
Tuomas Tynkkynen9acd5712018-04-20 13:03:49 +030092 * Older versions of the boot firmware place the firmware-loaded DTB at 0x100,
93 * newer versions place it in high memory. So prevent U-Boot from doing its own
94 * DTB + initrd relocation so that we won't accidentally relocate the initrd
95 * over the firmware-loaded DTB and generally try to lay out things starting
96 * from the bottom of RAM.
Stephen Warrend8845db2016-04-04 20:00:41 -060097 *
Tuomas Tynkkynen9acd5712018-04-20 13:03:49 +030098 * kernel_addr_r has different constraints on ARM and Aarch64. For 32-bit ARM,
99 * it must be within the first 128M of RAM in order for the kernel's
100 * CONFIG_AUTO_ZRELADDR option to work. The kernel itself will be decompressed
101 * to 0x8000 but the decompressor clobbers 0x4000-0x8000 as well. The
102 * decompressor also likes to relocate itself to right past the end of the
103 * decompressed kernel, so in total the sum of the compressed and and
104 * decompressed kernel needs to be reserved.
Stephen Warrend8845db2016-04-04 20:00:41 -0600105 *
Tuomas Tynkkynen9acd5712018-04-20 13:03:49 +0300106 * For Aarch64, the kernel image is uncompressed and must be loaded at
107 * text_offset bytes (specified in the header of the Image) into a 2MB
108 * boundary. The 'booti' command relocates the image if necessary. Linux uses
109 * a default text_offset of 0x80000. In summary, loading at 0x80000
110 * satisfies all these constraints and reserving memory up to 0x02400000
111 * permits fairly large (roughly 36M) kernels.
Stephen Warrend8845db2016-04-04 20:00:41 -0600112 *
Tuomas Tynkkynen9acd5712018-04-20 13:03:49 +0300113 * scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't
114 * conflict with something else. Reserving 1M for each of them at
115 * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty.
Stephen Warrend8845db2016-04-04 20:00:41 -0600116 *
Tuomas Tynkkynen9acd5712018-04-20 13:03:49 +0300117 * On ARM, both the DTB and any possible initrd must be loaded such that they
118 * fit inside the lowmem mapping in Linux. In practice, this usually means not
119 * more than ~700M away from the start of the kernel image but this number can
120 * be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line
121 * parameter given to the kernel. So reserving memory from low to high
122 * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for
123 * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000.
124 * Even with the smallest possible CPU-GPU memory split of the CPU getting
125 * only 64M, the remaining 25M starting at 0x02700000 should allow quite
126 * large initrds before they start colliding with U-Boot.
Stephen Warrend8845db2016-04-04 20:00:41 -0600127 */
128#define ENV_MEM_LAYOUT_SETTINGS \
Tuomas Tynkkynen8c62fc02018-04-20 13:03:48 +0300129 "fdt_high=" FDT_HIGH "\0" \
130 "initrd_high=" INITRD_HIGH "\0" \
Tuomas Tynkkynen9acd5712018-04-20 13:03:49 +0300131 "kernel_addr_r=0x00080000\0" \
132 "scriptaddr=0x02400000\0" \
133 "pxefile_addr_r=0x02500000\0" \
134 "fdt_addr_r=0x02600000\0" \
135 "ramdisk_addr_r=0x02700000\0"
Stephen Warrend8845db2016-04-04 20:00:41 -0600136
akaher2191d542019-04-11 05:23:50 +0000137#if CONFIG_IS_ENABLED(CMD_MMC)
138 #define BOOT_TARGET_MMC(func) \
139 func(MMC, mmc, 0) \
Mike Karels69e74f32021-10-27 22:26:15 +0000140 func(MMC, mmc, 1) \
141 func(MMC, mmc, 2)
akaher2191d542019-04-11 05:23:50 +0000142#else
143 #define BOOT_TARGET_MMC(func)
144#endif
145
146#if CONFIG_IS_ENABLED(CMD_USB)
147 #define BOOT_TARGET_USB(func) func(USB, usb, 0)
148#else
149 #define BOOT_TARGET_USB(func)
150#endif
151
152#if CONFIG_IS_ENABLED(CMD_PXE)
153 #define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
154#else
155 #define BOOT_TARGET_PXE(func)
156#endif
157
158#if CONFIG_IS_ENABLED(CMD_DHCP)
159 #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
160#else
161 #define BOOT_TARGET_DHCP(func)
162#endif
163
Stephen Warrend8845db2016-04-04 20:00:41 -0600164#define BOOT_TARGET_DEVICES(func) \
akaher2191d542019-04-11 05:23:50 +0000165 BOOT_TARGET_MMC(func) \
166 BOOT_TARGET_USB(func) \
167 BOOT_TARGET_PXE(func) \
168 BOOT_TARGET_DHCP(func)
169
Stephen Warrend8845db2016-04-04 20:00:41 -0600170#include <config_distro_bootcmd.h>
171
172#define CONFIG_EXTRA_ENV_SETTINGS \
173 "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \
174 ENV_DEVICE_SETTINGS \
Marek Szyprowski378f5932019-12-02 12:11:18 +0100175 ENV_DFU_SETTINGS \
Stephen Warrend8845db2016-04-04 20:00:41 -0600176 ENV_MEM_LAYOUT_SETTINGS \
177 BOOTENV
Alexander Stein50e81842015-07-24 09:22:11 +0200178
Stephen Warren0e012c32012-08-05 16:07:22 +0000179
Stephen Warren0e012c32012-08-05 16:07:22 +0000180#endif