| Nikita Kiryanov | b260492 | 2015-02-03 13:32:20 +0200 | [diff] [blame] | 1 | /* |
| 2 | * atmel_lcd.h - Atmel LCD Controller structures |
| 3 | * |
| 4 | * (C) Copyright 2001 |
| 5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef _ATMEL_LCD_H_ |
| 11 | #define _ATMEL_LCD_H_ |
| 12 | |
| 13 | typedef struct vidinfo { |
| 14 | ushort vl_col; /* Number of columns (i.e. 640) */ |
| 15 | ushort vl_row; /* Number of rows (i.e. 480) */ |
| 16 | u_long vl_clk; /* pixel clock in ps */ |
| 17 | |
| 18 | /* LCD configuration register */ |
| 19 | u_long vl_sync; /* Horizontal / vertical sync */ |
| 20 | u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ |
| 21 | u_long vl_tft; /* 0 = passive, 1 = TFT */ |
| 22 | u_long vl_cont_pol_low; /* contrast polarity is low */ |
| 23 | u_long vl_clk_pol; /* clock polarity */ |
| 24 | |
| 25 | /* Horizontal control register. */ |
| 26 | u_long vl_hsync_len; /* Length of horizontal sync */ |
| 27 | u_long vl_left_margin; /* Time from sync to picture */ |
| 28 | u_long vl_right_margin; /* Time from picture to sync */ |
| 29 | |
| 30 | /* Vertical control register. */ |
| 31 | u_long vl_vsync_len; /* Length of vertical sync */ |
| 32 | u_long vl_upper_margin; /* Time from sync to picture */ |
| 33 | u_long vl_lower_margin; /* Time from picture to sync */ |
| 34 | |
| 35 | u_long mmio; /* Memory mapped registers */ |
| 36 | } vidinfo_t; |
| 37 | |
| 38 | #endif |