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git01.mediatek.com / filogic / uboot / 69a5321c429773b672a053fd2087358eddec8882 / . / arch / arm / dts / imx6qdl-gw5907.dtsi
blob: a36b6e7048c79dcbb267d6f6f9f4e193606ba453 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 nand = &gpmi;
Tim Harvey69a53212021-07-24 10:40:36 -0700[diff] [blame^]16 usb0 = &usbotg;
17 usb1 = &usbh1;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]18 };
19
20 chosen {
21 stdout-path = &uart2;
22 };
23
24 gpio-keys {
25 compatible = "gpio-keys";
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 user-pb {
30 label = "user_pb";
31 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
32 linux,code = <BTN_0>;
33 };
34
35 user-pb1x {
36 label = "user_pb1x";
37 linux,code = <BTN_1>;
38 interrupt-parent = <&gsc>;
39 interrupts = <0>;
40 };
41
42 key-erased {
43 label = "key-erased";
44 linux,code = <BTN_2>;
45 interrupt-parent = <&gsc>;
46 interrupts = <1>;
47 };
48
49 eeprom-wp {
50 label = "eeprom_wp";
51 linux,code = <BTN_3>;
52 interrupt-parent = <&gsc>;
53 interrupts = <2>;
54 };
55
56 tamper {
57 label = "tamper";
58 linux,code = <BTN_4>;
59 interrupt-parent = <&gsc>;
60 interrupts = <5>;
61 };
62
63 switch-hold {
64 label = "switch_hold";
65 linux,code = <BTN_5>;
66 interrupt-parent = <&gsc>;
67 interrupts = <7>;
68 };
69 };
70
71 leds {
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_leds>;
75
76 led0: user1 {
77 label = "user1";
78 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
79 default-state = "on";
80 linux,default-trigger = "heartbeat";
81 };
82
83 led1: user2 {
84 label = "user2";
85 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
86 default-state = "off";
87 };
88 };
89
90 memory@10000000 {
91 device_type = "memory";
92 reg = <0x10000000 0x20000000>;
93 };
94
95 pps {
96 compatible = "pps-gpio";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_pps>;
99 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
100 status = "okay";
101 };
102
103 reg_3p3v: regulator-3p3v {
104 compatible = "regulator-fixed";
105 regulator-name = "3P3V";
106 regulator-min-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>;
108 regulator-always-on;
109 };
110
111 reg_5p0v: regulator-5p0v {
112 compatible = "regulator-fixed";
113 regulator-name = "5P0V";
114 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <5000000>;
116 regulator-always-on;
117 };
118
119 reg_usb_otg_vbus: regulator-usb-otg-vbus {
120 compatible = "regulator-fixed";
121 regulator-name = "usb_otg_vbus";
122 regulator-min-microvolt = <5000000>;
123 regulator-max-microvolt = <5000000>;
124 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
125 enable-active-high;
126 };
127};
128
129&fec {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_enet>;
132 phy-mode = "rgmii-id";
133 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
Tim Harvey6ce10d52021-05-03 11:21:27 -0700[diff] [blame]134 phy-reset-duration = <10>;
135 phy-reset-post-delay = <100>;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]136 status = "okay";
137};
138
139&gpmi {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_gpmi_nand>;
142 status = "okay";
143};
144
145&hdmi {
146 ddc-i2c-bus = <&i2c3>;
147 status = "okay";
148};
149
150&i2c1 {
151 clock-frequency = <100000>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c1>;
154 status = "okay";
155
156 gsc: gsc@20 {
157 compatible = "gw,gsc";
158 reg = <0x20>;
159 interrupt-parent = <&gpio1>;
160 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
161 interrupt-controller;
162 #interrupt-cells = <1>;
163 #size-cells = <0>;
164
165 adc {
166 compatible = "gw,gsc-adc";
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 channel@0 {
171 gw,mode = <0>;
172 reg = <0x00>;
173 label = "temp";
174 };
175
176 channel@2 {
177 gw,mode = <1>;
178 reg = <0x02>;
179 label = "vdd_vin";
180 };
181
182 channel@5 {
183 gw,mode = <1>;
184 reg = <0x05>;
185 label = "vdd_3p3";
186 };
187
188 channel@8 {
189 gw,mode = <1>;
190 reg = <0x08>;
191 label = "vdd_bat";
192 };
193
194 channel@b {
195 gw,mode = <1>;
196 reg = <0x0b>;
197 label = "vdd_5p0";
198 };
199
200 channel@e {
201 gw,mode = <1>;
202 reg = <0xe>;
203 label = "vdd_arm";
204 };
205
206 channel@11 {
207 gw,mode = <1>;
208 reg = <0x11>;
209 label = "vdd_soc";
210 };
211
212 channel@14 {
213 gw,mode = <1>;
214 reg = <0x14>;
215 label = "vdd_3p0";
216 };
217
218 channel@17 {
219 gw,mode = <1>;
220 reg = <0x17>;
221 label = "vdd_1p5";
222 };
223
224 channel@1d {
225 gw,mode = <1>;
226 reg = <0x1d>;
227 label = "vdd_1p8";
228 };
229
230 channel@20 {
231 gw,mode = <1>;
232 reg = <0x20>;
233 label = "vdd_an1";
234 };
235
236 channel@23 {
237 gw,mode = <1>;
238 reg = <0x23>;
239 label = "vdd_2p5";
240 };
241 };
242 };
243
244 gsc_gpio: gpio@23 {
245 compatible = "nxp,pca9555";
246 reg = <0x23>;
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-parent = <&gsc>;
250 interrupts = <4>;
251 };
252
253 eeprom@50 {
254 compatible = "atmel,24c02";
255 reg = <0x50>;
256 pagesize = <16>;
257 };
258
259 eeprom@51 {
260 compatible = "atmel,24c02";
261 reg = <0x51>;
262 pagesize = <16>;
263 };
264
265 eeprom@52 {
266 compatible = "atmel,24c02";
267 reg = <0x52>;
268 pagesize = <16>;
269 };
270
271 eeprom@53 {
272 compatible = "atmel,24c02";
273 reg = <0x53>;
274 pagesize = <16>;
275 };
276
277 ds1672@68 {
278 compatible = "dallas,ds1672";
279 reg = <0x68>;
280 };
281};
282
283&i2c2 {
284 clock-frequency = <100000>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_i2c2>;
287 status = "okay";
288};
289
290&i2c3 {
291 clock-frequency = <100000>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c3>;
294 status = "okay";
295
296 gpio@20 {
297 compatible = "nxp,pca9555";
298 reg = <0x20>;
299 gpio-controller;
300 #gpio-cells = <2>;
301 };
302
303 adc@48 {
304 compatible = "ti,ads1015";
305 reg = <0x48>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308
309 channel@4 {
310 reg = <4>;
311 ti,gain = <0>;
312 ti,datarate = <5>;
313 };
314
315 channel@5 {
316 reg = <5>;
317 ti,gain = <0>;
318 ti,datarate = <5>;
319 };
320
321 channel@6 {
322 reg = <6>;
323 ti,gain = <0>;
324 ti,datarate = <5>;
325 };
326 };
327};
328
329&pcie {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_pcie>;
332 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
333 status = "okay";
334};
335
336&pwm2 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
339 status = "disabled";
340};
341
342&pwm3 {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
345 status = "disabled";
346};
347
348&pwm4 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
351 status = "disabled";
352};
353
354&uart1 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_uart1>;
357 status = "okay";
358};
359
360&uart2 {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_uart2>;
363 status = "okay";
364};
365
366&uart3 {
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_uart3>;
369 status = "okay";
370};
371
372&uart5 {
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_uart5>;
375 status = "okay";
376};
377
378&usbotg {
379 vbus-supply = <&reg_usb_otg_vbus>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_usbotg>;
382 disable-over-current;
Tim Harvey3deb9892021-03-01 14:33:31 -0800[diff] [blame]383 dr_mode = "otg";
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]384 status = "okay";
385};
386
387&usbh1 {
388 status = "okay";
389};
390
391&wdog1 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_wdog>;
394 fsl,ext-reset-output;
395};
396
397&iomuxc {
398 pinctrl_enet: enetgrp {
399 fsl,pins = <
400 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
401 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
402 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
403 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
404 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
405 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
406 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
407 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
408 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
409 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
410 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
411 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
412 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
413 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
414 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
415 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
416 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
417 >;
418 };
419
420 pinctrl_gpio_leds: gpioledsgrp {
421 fsl,pins = <
422 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
423 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
424 >;
425 };
426
427 pinctrl_gpmi_nand: gpminandgrp {
428 fsl,pins = <
429 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
430 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
431 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
432 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
433 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
434 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
435 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
436 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
437 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
438 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
439 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
440 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
441 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
442 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
443 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
444 >;
445 };
446
447 pinctrl_i2c1: i2c1grp {
448 fsl,pins = <
449 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
450 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
451 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
452 >;
453 };
454
455 pinctrl_i2c2: i2c2grp {
456 fsl,pins = <
457 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
458 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
459 >;
460 };
461
462 pinctrl_i2c3: i2c3grp {
463 fsl,pins = <
464 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
465 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
466 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
467 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
468 >;
469 };
470
471 pinctrl_pcie: pciegrp {
472 fsl,pins = <
473 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
474 >;
475 };
476
477 pinctrl_pps: ppsgrp {
478 fsl,pins = <
479 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
480 >;
481 };
482
483 pinctrl_pwm2: pwm2grp {
484 fsl,pins = <
485 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
486 >;
487 };
488
489 pinctrl_pwm3: pwm3grp {
490 fsl,pins = <
491 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
492 >;
493 };
494
495 pinctrl_pwm4: pwm4grp {
496 fsl,pins = <
497 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
498 >;
499 };
500
501 pinctrl_uart1: uart1grp {
502 fsl,pins = <
503 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
504 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
505 >;
506 };
507
508 pinctrl_uart2: uart2grp {
509 fsl,pins = <
510 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
511 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
512 >;
513 };
514
515 pinctrl_uart3: uart3grp {
516 fsl,pins = <
517 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
518 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
519 >;
520 };
521
522 pinctrl_uart5: uart5grp {
523 fsl,pins = <
524 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
525 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
526 >;
527 };
528
529 pinctrl_usbotg: usbotggrp {
530 fsl,pins = <
531 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
532 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
533 >;
534 };
535
536 pinctrl_wdog: wdoggrp {
537 fsl,pins = <
538 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
539 >;
540 };
541};