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git01.mediatek.com / filogic / uboot / 6995a024b06e333adfdeb5e35e81aaf6d2c958ed / . / arch / powerpc / cpu / mpc85xx / p5040_serdes.c
blob: 890b88e4e337233e575923de2f8c2f98f57e1463 [file] [log] [blame]
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]1/*
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/fsl_serdes.h>
25#include <asm/processor.h>
26#include <asm/io.h>
27#include "fsl_corenet_serdes.h"
28
29/*
30 * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
31 * U-boot only supports one SerDes controller. Therefore, we ignore bank 4 in
32 * this table. This works because most of the SerDes code is for errata
33 * work-arounds, and there are no P5040 errata that effect bank 4.
34 */
35
36static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
37 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
38 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
39 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
40 XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
41 [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
42 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
43 XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
44 XAUI_FM2, /* SATA1, SATA2 */ },
45 [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
46 SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
47 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
48 XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
49 [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
50 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
51 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
52 SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
53 /* SATA1, SATA2 */ },
54 [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
55 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
56 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
57 SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
58 /* SATA1, SATA2 */ },
59 [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
60 SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
61 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
62 XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
63 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
64 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
65 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
66 XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
67 [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
68 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
69 XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
70 XAUI_FM2, /* SATA1, SATA2 */ },
71 [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
72 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
73 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
74 /* NONE, NONE */ },
75 [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
76 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
77 NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
78 [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
79 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
80 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
81 XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
82 [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
83 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
84 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
85 NONE, SATA1, SATA2, /* NONE, NONE */ },
86 [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
87 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
88 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
89 /* NONE, NONE */ },
90 [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
91 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
92 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
93 NONE, SATA1, SATA2, /* NONE, NONE */ },
94};
95
96enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
97{
98 if (!serdes_lane_enabled(lane))
99 return NONE;
100
101 return serdes_cfg_tbl[cfg][lane];
102}
103
104int is_serdes_prtcl_valid(u32 prtcl)
105{
106 int i;
107
108 if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
109 return 0;
110
111 for (i = 0; i < SRDS_MAX_LANES; i++) {
112 if (serdes_cfg_tbl[prtcl][i] != NONE)
113 return 1;
114 }
115
116 return 0;
117}