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git01.mediatek.com / filogic / uboot / 698a1f22dbf58325ce8fbfc9737d60de1c81265b / . / arch / arm / include / asm / arch-omap5 / clocks.h
blob: f32cf3eeef7beb8e79ef791b3945dc3155291087 [file] [log] [blame]
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]1/*
2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
4 *
5 * Aneesh V <aneesh@ti.com>
6 * Sricharan R <r.sricharan@ti.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26#ifndef _CLOCKS_OMAP5_H_
27#define _CLOCKS_OMAP5_H_
28#include <common.h>
29
30/*
31 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
32 * loop, allow for a minimum of 2 ms wait (in reality the wait will be
33 * much more than that)
34 */
35#define LDELAY 1000000
36
37#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
38#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
39#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
40#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
41
42struct omap5_prcm_regs {
43 /* cm1.ckgen */
44 u32 cm_clksel_core; /* 4a004100 */
45 u32 pad001[1]; /* 4a004104 */
46 u32 cm_clksel_abe; /* 4a004108 */
47 u32 pad002[1]; /* 4a00410c */
48 u32 cm_dll_ctrl; /* 4a004110 */
49 u32 pad003[3]; /* 4a004114 */
50 u32 cm_clkmode_dpll_core; /* 4a004120 */
51 u32 cm_idlest_dpll_core; /* 4a004124 */
52 u32 cm_autoidle_dpll_core; /* 4a004128 */
53 u32 cm_clksel_dpll_core; /* 4a00412c */
54 u32 cm_div_m2_dpll_core; /* 4a004130 */
55 u32 cm_div_m3_dpll_core; /* 4a004134 */
56 u32 cm_div_h11_dpll_core; /* 4a004138 */
57 u32 cm_div_h12_dpll_core; /* 4a00413c */
58 u32 cm_div_h13_dpll_core; /* 4a004140 */
59 u32 cm_div_h14_dpll_core; /* 4a004144 */
60 u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */
61 u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */
62 u32 cm_emu_override_dpll_core; /* 4a004150 */
63
64 u32 cm_div_h22_dpllcore; /* 4a004154 */
65 u32 cm_div_h23_dpll_core; /* 4a004158 */
66 u32 pad0041[1]; /* 4a00415c */
67 u32 cm_clkmode_dpll_mpu; /* 4a004160 */
68 u32 cm_idlest_dpll_mpu; /* 4a004164 */
69 u32 cm_autoidle_dpll_mpu; /* 4a004168 */
70 u32 cm_clksel_dpll_mpu; /* 4a00416c */
71 u32 cm_div_m2_dpll_mpu; /* 4a004170 */
72 u32 pad005[5]; /* 4a004174 */
73 u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */
74 u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */
75 u32 pad006[3]; /* 4a004190 */
76 u32 cm_bypclk_dpll_mpu; /* 4a00419c */
77 u32 cm_clkmode_dpll_iva; /* 4a0041a0 */
78 u32 cm_idlest_dpll_iva; /* 4a0041a4 */
79 u32 cm_autoidle_dpll_iva; /* 4a0041a8 */
80 u32 cm_clksel_dpll_iva; /* 4a0041ac */
81 u32 pad007[2]; /* 4a0041b0 */
82 u32 cm_div_h11_dpll_iva; /* 4a0041b8 */
83 u32 cm_div_h12_dpll_iva; /* 4a0041bc */
84 u32 pad008[2]; /* 4a0041c0 */
85 u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */
86 u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */
87 u32 pad009[3]; /* 4a0041d0 */
88 u32 cm_bypclk_dpll_iva; /* 4a0041dc */
89 u32 cm_clkmode_dpll_abe; /* 4a0041e0 */
90 u32 cm_idlest_dpll_abe; /* 4a0041e4 */
91 u32 cm_autoidle_dpll_abe; /* 4a0041e8 */
92 u32 cm_clksel_dpll_abe; /* 4a0041ec */
93 u32 cm_div_m2_dpll_abe; /* 4a0041f0 */
94 u32 cm_div_m3_dpll_abe; /* 4a0041f4 */
95 u32 pad010[4]; /* 4a0041f8 */
96 u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */
97 u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */
98 u32 pad011[4]; /* 4a004210 */
99 u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */
100 u32 cm_idlest_dpll_ddrphy; /* 4a004224 */
101 u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */
102 u32 cm_clksel_dpll_ddrphy; /* 4a00422c */
103 u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */
104 u32 pad012[1]; /* 4a004234 */
105 u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */
106 u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */
107 u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */
108 u32 pad013[1]; /* 4a004244 */
109 u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */
110 u32 pad014[5]; /* 4a00424c */
111 u32 cm_shadow_freq_config1; /* 4a004260 */
112 u32 pad0141[47]; /* 4a004264 */
113 u32 cm_mpu_mpu_clkctrl; /* 4a004320 */
114
115
116 /* cm1.dsp */
117 u32 pad015[55]; /* 4a004324 */
118 u32 cm_dsp_clkstctrl; /* 4a004400 */
119 u32 pad016[7]; /* 4a004404 */
120 u32 cm_dsp_dsp_clkctrl; /* 4a004420 */
121
122 /* cm1.abe */
123 u32 pad017[55]; /* 4a004424 */
124 u32 cm1_abe_clkstctrl; /* 4a004500 */
125 u32 pad018[7]; /* 4a004504 */
126 u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */
127 u32 pad019[1]; /* 4a004524 */
128 u32 cm1_abe_aess_clkctrl; /* 4a004528 */
129 u32 pad020[1]; /* 4a00452c */
130 u32 cm1_abe_pdm_clkctrl; /* 4a004530 */
131 u32 pad021[1]; /* 4a004534 */
132 u32 cm1_abe_dmic_clkctrl; /* 4a004538 */
133 u32 pad022[1]; /* 4a00453c */
134 u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */
135 u32 pad023[1]; /* 4a004544 */
136 u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */
137 u32 pad024[1]; /* 4a00454c */
138 u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */
139 u32 pad025[1]; /* 4a004554 */
140 u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */
141 u32 pad026[1]; /* 4a00455c */
142 u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */
143 u32 pad027[1]; /* 4a004564 */
144 u32 cm1_abe_timer5_clkctrl; /* 4a004568 */
145 u32 pad028[1]; /* 4a00456c */
146 u32 cm1_abe_timer6_clkctrl; /* 4a004570 */
147 u32 pad029[1]; /* 4a004574 */
148 u32 cm1_abe_timer7_clkctrl; /* 4a004578 */
149 u32 pad030[1]; /* 4a00457c */
150 u32 cm1_abe_timer8_clkctrl; /* 4a004580 */
151 u32 pad031[1]; /* 4a004584 */
152 u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */
153
154 /* cm2.ckgen */
155 u32 pad032[3805]; /* 4a00458c */
156 u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */
157 u32 cm_clksel_usb_60mhz; /* 4a008104 */
158 u32 cm_scale_fclk; /* 4a008108 */
159 u32 pad033[1]; /* 4a00810c */
160 u32 cm_core_dvfs_perf1; /* 4a008110 */
161 u32 cm_core_dvfs_perf2; /* 4a008114 */
162 u32 cm_core_dvfs_perf3; /* 4a008118 */
163 u32 cm_core_dvfs_perf4; /* 4a00811c */
164 u32 pad034[1]; /* 4a008120 */
165 u32 cm_core_dvfs_current; /* 4a008124 */
166 u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */
167 u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */
168 u32 cm_iva_dvfs_perf_abe; /* 4a008130 */
169 u32 pad035[1]; /* 4a008134 */
170 u32 cm_iva_dvfs_current; /* 4a008138 */
171 u32 pad036[1]; /* 4a00813c */
172 u32 cm_clkmode_dpll_per; /* 4a008140 */
173 u32 cm_idlest_dpll_per; /* 4a008144 */
174 u32 cm_autoidle_dpll_per; /* 4a008148 */
175 u32 cm_clksel_dpll_per; /* 4a00814c */
176 u32 cm_div_m2_dpll_per; /* 4a008150 */
177 u32 cm_div_m3_dpll_per; /* 4a008154 */
178 u32 cm_div_h11_dpll_per; /* 4a008158 */
179 u32 cm_div_h12_dpll_per; /* 4a00815c */
180 u32 pad0361[1]; /* 4a008160 */
181 u32 cm_div_h14_dpll_per; /* 4a008164 */
182 u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */
183 u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */
184 u32 cm_emu_override_dpll_per; /* 4a008170 */
185 u32 pad037[3]; /* 4a008174 */
186 u32 cm_clkmode_dpll_usb; /* 4a008180 */
187 u32 cm_idlest_dpll_usb; /* 4a008184 */
188 u32 cm_autoidle_dpll_usb; /* 4a008188 */
189 u32 cm_clksel_dpll_usb; /* 4a00818c */
190 u32 cm_div_m2_dpll_usb; /* 4a008190 */
191 u32 pad038[5]; /* 4a008194 */
192 u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */
193 u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */
194 u32 pad039[1]; /* 4a0081b0 */
195 u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */
196 u32 pad040[2]; /* 4a0081b8 */
197 u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */
198 u32 cm_idlest_dpll_unipro; /* 4a0081c4 */
199 u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */
200 u32 cm_clksel_dpll_unipro; /* 4a0081cc */
201 u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */
202 u32 pad041[5]; /* 4a0081d4 */
203 u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */
204 u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */
205
206 /* cm2.core */
207 u32 pad0411[324]; /* 4a0081f0 */
208 u32 cm_l3_1_clkstctrl; /* 4a008700 */
209 u32 pad042[1]; /* 4a008704 */
210 u32 cm_l3_1_dynamicdep; /* 4a008708 */
211 u32 pad043[5]; /* 4a00870c */
212 u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */
213 u32 pad044[55]; /* 4a008724 */
214 u32 cm_l3_2_clkstctrl; /* 4a008800 */
215 u32 pad045[1]; /* 4a008804 */
216 u32 cm_l3_2_dynamicdep; /* 4a008808 */
217 u32 pad046[5]; /* 4a00880c */
218 u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */
219 u32 pad047[1]; /* 4a008824 */
220 u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */
221 u32 pad048[1]; /* 4a00882c */
222 u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */
223 u32 pad049[51]; /* 4a008834 */
224 u32 cm_mpu_m3_clkstctrl; /* 4a008900 */
225 u32 cm_mpu_m3_staticdep; /* 4a008904 */
226 u32 cm_mpu_m3_dynamicdep; /* 4a008908 */
227 u32 pad050[5]; /* 4a00890c */
228 u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */
229 u32 pad051[55]; /* 4a008924 */
230 u32 cm_sdma_clkstctrl; /* 4a008a00 */
231 u32 cm_sdma_staticdep; /* 4a008a04 */
232 u32 cm_sdma_dynamicdep; /* 4a008a08 */
233 u32 pad052[5]; /* 4a008a0c */
234 u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */
235 u32 pad053[55]; /* 4a008a24 */
236 u32 cm_memif_clkstctrl; /* 4a008b00 */
237 u32 pad054[7]; /* 4a008b04 */
238 u32 cm_memif_dmm_clkctrl; /* 4a008b20 */
239 u32 pad055[1]; /* 4a008b24 */
240 u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */
241 u32 pad056[1]; /* 4a008b2c */
242 u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */
243 u32 pad057[1]; /* 4a008b34 */
244 u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */
245 u32 pad058[1]; /* 4a008b3c */
246 u32 cm_memif_dll_clkctrl; /* 4a008b40 */
247 u32 pad059[3]; /* 4a008b44 */
248 u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */
249 u32 pad060[1]; /* 4a008b54 */
250 u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */
251 u32 pad061[1]; /* 4a008b5c */
252 u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */
253 u32 pad062[39]; /* 4a008b64 */
254 u32 cm_c2c_clkstctrl; /* 4a008c00 */
255 u32 cm_c2c_staticdep; /* 4a008c04 */
256 u32 cm_c2c_dynamicdep; /* 4a008c08 */
257 u32 pad063[5]; /* 4a008c0c */
258 u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */
259 u32 pad064[1]; /* 4a008c24 */
260 u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */
261 u32 pad065[1]; /* 4a008c2c */
262 u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */
263 u32 pad066[51]; /* 4a008c34 */
264 u32 cm_l4cfg_clkstctrl; /* 4a008d00 */
265 u32 pad067[1]; /* 4a008d04 */
266 u32 cm_l4cfg_dynamicdep; /* 4a008d08 */
267 u32 pad068[5]; /* 4a008d0c */
268 u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */
269 u32 pad069[1]; /* 4a008d24 */
270 u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */
271 u32 pad070[1]; /* 4a008d2c */
272 u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */
273 u32 pad071[1]; /* 4a008d34 */
274 u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */
275 u32 pad072[49]; /* 4a008d3c */
276 u32 cm_l3instr_clkstctrl; /* 4a008e00 */
277 u32 pad073[7]; /* 4a008e04 */
278 u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */
279 u32 pad074[1]; /* 4a008e24 */
280 u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */
281 u32 pad075[5]; /* 4a008e2c */
282 u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */
283
284
285 /* cm2.ivahd */
286 u32 pad076[47]; /* 4a008e44 */
287 u32 cm_ivahd_clkstctrl; /* 4a008f00 */
288 u32 pad077[7]; /* 4a008f04 */
289 u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */
290 u32 pad078[1]; /* 4a008f24 */
291 u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */
292
293 /* cm2.cam */
294 u32 pad079[53]; /* 4a008f2c */
295 u32 cm_cam_clkstctrl; /* 4a009000 */
296 u32 pad080[7]; /* 4a009004 */
297 u32 cm_cam_iss_clkctrl; /* 4a009020 */
298 u32 pad081[1]; /* 4a009024 */
299 u32 cm_cam_fdif_clkctrl; /* 4a009028 */
300
301 /* cm2.dss */
302 u32 pad082[53]; /* 4a00902c */
303 u32 cm_dss_clkstctrl; /* 4a009100 */
304 u32 pad083[7]; /* 4a009104 */
305 u32 cm_dss_dss_clkctrl; /* 4a009120 */
306
307 /* cm2.sgx */
308 u32 pad084[55]; /* 4a009124 */
309 u32 cm_sgx_clkstctrl; /* 4a009200 */
310 u32 pad085[7]; /* 4a009204 */
311 u32 cm_sgx_sgx_clkctrl; /* 4a009220 */
312
313 /* cm2.l3init */
314 u32 pad086[55]; /* 4a009224 */
315 u32 cm_l3init_clkstctrl; /* 4a009300 */
316
317 /* cm2.l3init */
318 u32 pad087[9]; /* 4a009304 */
319 u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */
320 u32 pad088[1]; /* 4a00932c */
321 u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */
322 u32 pad089[1]; /* 4a009334 */
323 u32 cm_l3init_hsi_clkctrl; /* 4a009338 */
324 u32 pad090[7]; /* 4a00933c */
325 u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */
326 u32 pad091[1]; /* 4a00935c */
327 u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */
328 u32 pad092[1]; /* 4a009364 */
329 u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */
330 u32 pad093[3]; /* 4a00936c */
331 u32 cm_l3init_p1500_clkctrl; /* 4a009378 */
332 u32 pad094[21]; /* 4a00937c */
333 u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */
334 u32 pad095[3]; /* 4a0093d4 */
335 u32 cm_l3init_ocp2scp1_clkctrl;
336
337 /* cm2.l4per */
338 u32 pad096[7]; /* 4a0093e4 */
339 u32 cm_l4per_clkstctrl; /* 4a009400 */
340 u32 pad097[1]; /* 4a009404 */
341 u32 cm_l4per_dynamicdep; /* 4a009408 */
342 u32 pad098[5]; /* 4a00940c */
343 u32 cm_l4per_adc_clkctrl; /* 4a009420 */
344 u32 pad100[1]; /* 4a009424 */
345 u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */
346 u32 pad101[1]; /* 4a00942c */
347 u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */
348 u32 pad102[1]; /* 4a009434 */
349 u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */
350 u32 pad103[1]; /* 4a00943c */
351 u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */
352 u32 pad104[1]; /* 4a009444 */
353 u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */
354 u32 pad105[1]; /* 4a00944c */
355 u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */
356 u32 pad106[1]; /* 4a009454 */
357 u32 cm_l4per_elm_clkctrl; /* 4a009458 */
358 u32 pad107[1]; /* 4a00945c */
359 u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */
360 u32 pad108[1]; /* 4a009464 */
361 u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */
362 u32 pad109[1]; /* 4a00946c */
363 u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */
364 u32 pad110[1]; /* 4a009474 */
365 u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */
366 u32 pad111[1]; /* 4a00947c */
367 u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */
368 u32 pad112[1]; /* 4a009484 */
369 u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */
370 u32 pad113[1]; /* 4a00948c */
371 u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */
372 u32 pad114[1]; /* 4a009494 */
373 u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */
374 u32 pad115[1]; /* 4a00949c */
375 u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */
376 u32 pad116[1]; /* 4a0094a4 */
377 u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */
378 u32 pad117[1]; /* 4a0094ac */
379 u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */
380 u32 pad118[1]; /* 4a0094b4 */
381 u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */
382 u32 pad119[1]; /* 4a0094bc */
383 u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */
384 u32 pad1191[3]; /* 4a0094c4 */
385 u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */
386 u32 pad120[1]; /* 4a0094d4 */
387 u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */
388 u32 pad121[3]; /* 4a0094dc */
389 u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */
390 u32 pad123[1]; /* 4a0094ec */
391 u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */
392 u32 pad124[1]; /* 4a0094f4 */
393 u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */
394 u32 pad125[1]; /* 4a0094fc */
395 u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */
396 u32 pad126[1]; /* 4a009504 */
397 u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */
398 u32 pad127[1]; /* 4a00950c */
399 u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */
400 u32 pad1271[1]; /* 4a009514 */
401 u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */
402 u32 pad1272[1]; /* 4a00951c */
403 u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */
404 u32 pad128[1]; /* 4a009524 */
405 u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */
406 u32 pad129[1]; /* 4a00952c */
407 u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */
408 u32 pad130[1]; /* 4a009534 */
409 u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */
410 u32 pad131[1]; /* 4a00953c */
411 u32 cm_l4per_uart1_clkctrl; /* 4a009540 */
412 u32 pad132[1]; /* 4a009544 */
413 u32 cm_l4per_uart2_clkctrl; /* 4a009548 */
414 u32 pad133[1]; /* 4a00954c */
415 u32 cm_l4per_uart3_clkctrl; /* 4a009550 */
416 u32 pad134[1]; /* 4a009554 */
417 u32 cm_l4per_uart4_clkctrl; /* 4a009558 */
418 u32 pad135[1]; /* 4a00955c */
419 u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */
420 u32 pad136[1]; /* 4a009564 */
421 u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */
422 u32 pad1371[1]; /* 4a00956c */
423 u32 cm_l4per_uart5_clkctrl; /* 4a009570 */
424 u32 pad1372[1]; /* 4a009574 */
425 u32 cm_l4per_uart6_clkctrl; /* 4a009578 */
426 u32 pad1374[1]; /* 4a00957c */
427 u32 cm_l4sec_clkstctrl; /* 4a009580 */
428 u32 cm_l4sec_staticdep; /* 4a009584 */
429 u32 cm_l4sec_dynamicdep; /* 4a009588 */
430 u32 pad138[5]; /* 4a00958c */
431 u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */
432 u32 pad139[1]; /* 4a0095a4 */
433 u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */
434 u32 pad140[1]; /* 4a0095ac */
435 u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */
436 u32 pad141[1]; /* 4a0095b4 */
437 u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */
438 u32 pad142[1]; /* 4a0095bc */
439 u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */
440 u32 pad143[1]; /* 4a0095c4 */
441 u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */
442 u32 pad144[3]; /* 4a0095cc */
443 u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */
444 u32 pad145[3660425]; /* 4a0095dc */
445
446 /* l4 wkup regs */
447 u32 pad201[6211]; /* 4ae00000 */
448 u32 cm_abe_pll_ref_clksel; /* 4ae0610c */
449 u32 cm_sys_clksel; /* 4ae06110 */
450 u32 pad202[1467]; /* 4ae06114 */
451 u32 cm_wkup_clkstctrl; /* 4ae07800 */
452 u32 pad203[7]; /* 4ae07804 */
453 u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */
454 u32 pad204; /* 4ae07824 */
455 u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */
456 u32 pad205; /* 4ae0782c */
457 u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */
458 u32 pad206; /* 4ae07834 */
459 u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */
460 u32 pad207; /* 4ae0783c */
461 u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */
462 u32 pad208; /* 4ae07844 */
463 u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */
464 u32 pad209; /* 4ae0784c */
465 u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */
466 u32 pad210; /* 4ae07854 */
467 u32 cm_wkup_usim_clkctrl; /* 4ae07858 */
468 u32 pad211; /* 4ae0785c */
469 u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */
470 u32 pad212[5]; /* 4ae07864 */
471 u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */
472 u32 pad213; /* 4ae0787c */
473 u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */
474 u32 pad214; /* 4ae07884 */
475 u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */
SRICHARAN Rb1ee0bc2012-03-12 02:25:34 +0000[diff] [blame]476 u32 pad215[1]; /* 4ae0788c */
477 u32 cm_wkupaon_scrm_clkctrl; /* 4ae07890 */
478 u32 pad216[195];
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]479 u32 prm_vc_val_bypass; /* 4ae07ba0 */
SRICHARAN Rb1ee0bc2012-03-12 02:25:34 +0000[diff] [blame]480 u32 pad217[4];
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]481 u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
482 u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
483};
484
485/* DPLL register offsets */
486#define CM_CLKMODE_DPLL 0
487#define CM_IDLEST_DPLL 0x4
488#define CM_AUTOIDLE_DPLL 0x8
489#define CM_CLKSEL_DPLL 0xC
490
491#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
492
493/* CM_CLKMODE_DPLL */
494#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
495#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
496#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
497#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
498#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
499#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
500#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
501#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
502#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
503#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
504#define CM_CLKMODE_DPLL_EN_SHIFT 0
505#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
506
507#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
508#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
509
510#define DPLL_EN_STOP 1
511#define DPLL_EN_MN_BYPASS 4
512#define DPLL_EN_LOW_POWER_BYPASS 5
513#define DPLL_EN_FAST_RELOCK_BYPASS 6
514#define DPLL_EN_LOCK 7
515
516/* CM_IDLEST_DPLL fields */
517#define ST_DPLL_CLK_MASK 1
518
SRICHARAN Rb1ee0bc2012-03-12 02:25:34 +0000[diff] [blame]519/* SGX */
520#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
521#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
522
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]523/* CM_CLKSEL_DPLL */
524#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
525#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
526#define CM_CLKSEL_DPLL_M_SHIFT 8
527#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
528#define CM_CLKSEL_DPLL_N_SHIFT 0
529#define CM_CLKSEL_DPLL_N_MASK 0x7F
530#define CM_CLKSEL_DCC_EN_SHIFT 22
531#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
532
533#define OMAP4_DPLL_MAX_N 127
534
535/* CM_SYS_CLKSEL */
536#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
537
538/* CM_CLKSEL_CORE */
539#define CLKSEL_CORE_SHIFT 0
540#define CLKSEL_L3_SHIFT 4
541#define CLKSEL_L4_SHIFT 8
542
543#define CLKSEL_CORE_X2_DIV_1 0
544#define CLKSEL_L3_CORE_DIV_2 1
545#define CLKSEL_L4_L3_DIV_2 1
546
547/* CM_ABE_PLL_REF_CLKSEL */
548#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
549#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
550#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
551#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
552
553/* CM_BYPCLK_DPLL_IVA */
554#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
555#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
556
557#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
558
559/* CM_SHADOW_FREQ_CONFIG1 */
560#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
561#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
562#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
563
564#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
565#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
566
567#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
568#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
569
570/*CM_<clock_domain>__CLKCTRL */
571#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
572#define CD_CLKCTRL_CLKTRCTRL_MASK 3
573
574#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
575#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
576#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
577#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
578
579
580/* CM_<clock_domain>_<module>_CLKCTRL */
581#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
582#define MODULE_CLKCTRL_MODULEMODE_MASK 3
583#define MODULE_CLKCTRL_IDLEST_SHIFT 16
584#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
585
586#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
587#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
588#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
589
590#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
591#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
592#define MODULE_CLKCTRL_IDLEST_IDLE 2
593#define MODULE_CLKCTRL_IDLEST_DISABLED 3
594
595/* CM_L4PER_GPIO4_CLKCTRL */
596#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
597
598/* CM_L3INIT_HSMMCn_CLKCTRL */
599#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
SRICHARAN Rb1ee0bc2012-03-12 02:25:34 +0000[diff] [blame]600#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]601
602/* CM_WKUP_GPTIMER1_CLKCTRL */
603#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
604
605/* CM_CAM_ISS_CLKCTRL */
606#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
607
608/* CM_DSS_DSS_CLKCTRL */
609#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
610
611/* CM_L3INIT_USBPHY_CLKCTRL */
612#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
613
614/* CM_MPU_MPU_CLKCTRL */
615#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
616#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
617#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
618#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
619
SRICHARAN Rb1ee0bc2012-03-12 02:25:34 +0000[diff] [blame]620/* CM_WKUPAON_SCRM_CLKCTRL */
621#define OPTFCLKEN_SCRM_PER_SHIFT 9
622#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
623#define OPTFCLKEN_SCRM_CORE_SHIFT 8
624#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
625
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]626/* Clock frequencies */
627#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
628#define OMAP_SYS_CLK_IND_38_4_MHZ 6
629#define OMAP_32K_CLK_FREQ 32768
630
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]631/* PRM_VC_VAL_BYPASS */
632#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
633
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]634/* SMPS */
635#define SMPS_I2C_SLAVE_ADDR 0x12
SRICHARAN R698a1f22012-03-12 02:25:38 +0000[diff] [blame^]636#define SMPS_REG_ADDR_12_MPU 0x23
637#define SMPS_REG_ADDR_45_IVA 0x2B
638#define SMPS_REG_ADDR_8_CORE 0x37
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]639
SRICHARAN R698a1f22012-03-12 02:25:38 +0000[diff] [blame^]640/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
641#define VDD_MPU 1000
642#define VDD_MM 1000
643#define VDD_CORE 1040
644
645/* Standard offset is 0.5v expressed in uv */
646#define PALMAS_SMPS_BASE_VOLT_UV 500000
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]647
648/* TPS */
649#define TPS62361_I2C_SLAVE_ADDR 0x60
650#define TPS62361_REG_ADDR_SET0 0x0
651#define TPS62361_REG_ADDR_SET1 0x1
652#define TPS62361_REG_ADDR_SET2 0x2
653#define TPS62361_REG_ADDR_SET3 0x3
654#define TPS62361_REG_ADDR_CTRL 0x4
655#define TPS62361_REG_ADDR_TEMP 0x5
656#define TPS62361_REG_ADDR_RMP_CTRL 0x6
657#define TPS62361_REG_ADDR_CHIP_ID 0x8
658#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
659
660#define TPS62361_BASE_VOLT_MV 500
661#define TPS62361_VSEL0_GPIO 7
662
663/* Defines for DPLL setup */
664#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
665#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
666#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
667
668#define DPLL_NO_LOCK 0
669#define DPLL_LOCK 1
670
671#define NUM_SYS_CLKS 7
672
673struct dpll_regs {
674 u32 cm_clkmode_dpll;
675 u32 cm_idlest_dpll;
676 u32 cm_autoidle_dpll;
677 u32 cm_clksel_dpll;
678 u32 cm_div_m2_dpll;
679 u32 cm_div_m3_dpll;
680 u32 cm_div_h11_dpll;
681 u32 cm_div_h12_dpll;
682 u32 cm_div_h13_dpll;
683 u32 cm_div_h14_dpll;
SRICHARAN Rb1ee0bc2012-03-12 02:25:34 +0000[diff] [blame]684 u32 reserved[3];
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]685 u32 cm_div_h22_dpll;
686 u32 cm_div_h23_dpll;
687};
688
689/* DPLL parameter table */
690struct dpll_params {
691 u32 m;
692 u32 n;
Anatolij Gustschin625f6032011-12-03 06:46:15 +0000[diff] [blame]693 s8 m2;
694 s8 m3;
695 s8 h11;
696 s8 h12;
697 s8 h13;
698 s8 h14;
699 s8 h22;
700 s8 h23;
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]701};
702
703extern struct omap5_prcm_regs *const prcm;
704extern const u32 sys_clk_array[8];
705
706void scale_vcores(void);
Nishanth Menona0f45c12012-03-01 14:17:38 +0000[diff] [blame]707void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
SRICHARAN R698a1f22012-03-12 02:25:38 +0000[diff] [blame^]708u32 get_offset_code(u32 offset);
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]709u32 omap_ddr_clk(void);
710void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]711void setup_post_dividers(u32 *const base, const struct dpll_params *params);
712u32 get_sys_clk_index(void);
713void enable_basic_clocks(void);
714void enable_non_essential_clocks(void);
Sricharan308fe922011-11-15 09:50:03 -0500[diff] [blame]715void enable_basic_uboot_clocks(void);
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]716void do_enable_clocks(u32 *const *clk_domains,
717 u32 *const *clk_modules_hw_auto,
718 u32 *const *clk_modules_explicit_en,
719 u8 wait_for_enable);
720const struct dpll_params *get_mpu_dpll_params(void);
721const struct dpll_params *get_core_dpll_params(void);
722const struct dpll_params *get_per_dpll_params(void);
723const struct dpll_params *get_iva_dpll_params(void);
724const struct dpll_params *get_usb_dpll_params(void);
725const struct dpll_params *get_abe_dpll_params(void);
726#endif /* _CLOCKS_OMAP5_H_ */