| Kever Yang | bb33773 | 2019-07-22 20:02:01 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2019 Rockchip Electronics Co., Ltd. |
| 4 | */ |
| 5 | #include <common.h> |
| 6 | #include <clk.h> |
| 7 | #include <dm.h> |
| 8 | #include <ram.h> |
| 9 | #include <syscon.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <asm/arch-rockchip/boot_mode.h> |
| 12 | #include <asm/arch-rockchip/clock.h> |
| 13 | #include <asm/arch-rockchip/periph.h> |
| 14 | #include <power/regulator.h> |
| 15 | |
| 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
| 18 | __weak int rk_board_late_init(void) |
| 19 | { |
| 20 | return 0; |
| 21 | } |
| 22 | |
| 23 | int board_late_init(void) |
| 24 | { |
| 25 | setup_boot_mode(); |
| 26 | |
| 27 | return rk_board_late_init(); |
| 28 | } |
| 29 | |
| 30 | int board_init(void) |
| 31 | { |
| 32 | int ret; |
| 33 | |
| 34 | #ifdef CONFIG_DM_REGULATOR |
| 35 | ret = regulators_enable_boot_on(false); |
| 36 | if (ret) |
| 37 | debug("%s: Cannot enable boot on regulator\n", __func__); |
| 38 | #endif |
| 39 | |
| 40 | return 0; |
| 41 | } |
| 42 | |
| 43 | #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) |
| 44 | void enable_caches(void) |
| 45 | { |
| 46 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 47 | dcache_enable(); |
| 48 | } |
| 49 | #endif |
| 50 | |
| 51 | #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) |
| 52 | #include <usb.h> |
| 53 | #include <usb/dwc2_udc.h> |
| 54 | |
| 55 | static struct dwc2_plat_otg_data otg_data = { |
| 56 | .rx_fifo_sz = 512, |
| 57 | .np_tx_fifo_sz = 16, |
| 58 | .tx_fifo_sz = 128, |
| 59 | }; |
| 60 | |
| 61 | int board_usb_init(int index, enum usb_init_type init) |
| 62 | { |
| 63 | int node; |
| 64 | const char *mode; |
| 65 | bool matched = false; |
| 66 | const void *blob = gd->fdt_blob; |
| 67 | |
| 68 | /* find the usb_otg node */ |
| 69 | node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); |
| 70 | |
| 71 | while (node > 0) { |
| 72 | mode = fdt_getprop(blob, node, "dr_mode", NULL); |
| 73 | if (mode && strcmp(mode, "otg") == 0) { |
| 74 | matched = true; |
| 75 | break; |
| 76 | } |
| 77 | |
| 78 | node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2"); |
| 79 | } |
| 80 | if (!matched) { |
| 81 | debug("Not found usb_otg device\n"); |
| 82 | return -ENODEV; |
| 83 | } |
| 84 | otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); |
| 85 | |
| 86 | return dwc2_udc_probe(&otg_data); |
| 87 | } |
| 88 | |
| 89 | int board_usb_cleanup(int index, enum usb_init_type init) |
| 90 | { |
| 91 | return 0; |
| 92 | } |
| 93 | #endif |
| 94 | |
| 95 | #if CONFIG_IS_ENABLED(FASTBOOT) |
| 96 | int fastboot_set_reboot_flag(void) |
| 97 | { |
| 98 | printf("Setting reboot to fastboot flag ...\n"); |
| 99 | /* Set boot mode to fastboot */ |
| 100 | writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | #endif |