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git01.mediatek.com / filogic / uboot / 6986d6b9fea7849b61a0316b218523e707d0b3ef / . / include / configs / sama5d3_xplained.h
blob: 696933da73d00b30e4136da83c47a36ac90fd2a6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]2/*
3 * Configuration settings for the SAMA5D3 Xplained board.
4 *
5 * Copyright (C) 2014 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Wu, Josh42587542015-03-30 14:51:19 +0800[diff] [blame]12#include "at91-sama5_common.h"
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]13
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]14/*
15 * This needs to be defined for the OHCI code to work but it is defined as
16 * ATMEL_ID_UHPHS in the CPU specific header files.
17 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]18#define ATMEL_ID_UHP 32
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]19
20/*
21 * Specify the clock enable bit in the PMC_SCER register.
22 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]23#define ATMEL_PMC_UHP (1 << 6)
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]24
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]25/* SDRAM */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]26#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]27#define CONFIG_SYS_SDRAM_SIZE 0x10000000
28
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]29#ifdef CONFIG_SPL_BUILD
Wenyou Yang9ddd6fc2017-04-14 08:51:45 +0800[diff] [blame]30#define CONFIG_SYS_INIT_SP_ADDR 0x318000
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]31#else
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]32#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang9ddd6fc2017-04-14 08:51:45 +0800[diff] [blame]33 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]34#endif
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]35
36/* NAND flash */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]37#ifdef CONFIG_CMD_NAND
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]38#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]39#define CONFIG_SYS_NAND_BASE 0x60000000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]40/* our ALE is AD21 */
41#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
42/* our CLE is AD22 */
43#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
44#define CONFIG_SYS_NAND_ONFI_DETECTION
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]45#endif
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]46
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]47/* USB */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]48#ifdef CONFIG_CMD_USB
49#define CONFIG_USB_ATMEL
50#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
51#define CONFIG_USB_OHCI_NEW
52#define CONFIG_SYS_USB_OHCI_CPU_INIT
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]53#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]54#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
55#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]56#endif
57
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]58#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
59
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]60/* SPL */
Wenyou Yang9ddd6fc2017-04-14 08:51:45 +0800[diff] [blame]61#define CONFIG_SPL_MAX_SIZE 0x18000
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]62#define CONFIG_SPL_BSS_START_ADDR 0x20000000
63#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
64#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
65#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
66
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]67#define CONFIG_SYS_MONITOR_LEN (512 << 10)
68
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]69#ifdef CONFIG_SD_BOOT
Paul Kocialkowski341e8cd2014-11-08 23:14:55 +0100[diff] [blame]70#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET602a16c2014-10-15 17:53:11 +0200[diff] [blame]71#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]72
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]73#elif CONFIG_NAND_BOOT
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]74#define CONFIG_SPL_NAND_DRIVERS
75#define CONFIG_SPL_NAND_BASE
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]76#endif
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]77#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
78#define CONFIG_SYS_NAND_5_ADDR_CYCLE
79#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
80#define CONFIG_SYS_NAND_PAGE_COUNT 64
81#define CONFIG_SYS_NAND_OOBSIZE 64
82#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
83#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
84
85#endif