blob: 35866e096a3294ada1e285687d01062dd00daf50 [file] [log] [blame]
Igor Opaniuk309e65b2020-01-28 14:42:25 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2020 Toradex
4 */
5
6#include <common.h>
7#include <asm/arch/clock.h>
Igor Opaniukd1b4d0d2020-03-27 12:28:18 +02008#include <asm/arch/sys_proto.h>
Igor Opaniuk309e65b2020-01-28 14:42:25 +01009#include <asm/io.h>
10#include <miiphy.h>
11#include <netdev.h>
Philippe Schenkerbd0d5c02020-03-11 11:59:24 +010012#include <micrel.h>
Igor Opaniuk309e65b2020-01-28 14:42:25 +010013
14DECLARE_GLOBAL_DATA_PTR;
15
16int dram_init(void)
17{
Igor Opaniukd1b4d0d2020-03-27 12:28:18 +020018 /* rom_pointer[1] contains the size of TEE occupies */
19 if (rom_pointer[1])
20 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
21 else
22 gd->ram_size = PHYS_SDRAM_SIZE;
Igor Opaniuk309e65b2020-01-28 14:42:25 +010023
24 return 0;
25}
26
27#if IS_ENABLED(CONFIG_FEC_MXC)
28static int setup_fec(void)
29{
30 struct iomuxc_gpr_base_regs *gpr =
31 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
32
33 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
34 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
35
36 return 0;
37}
38
39int board_phy_config(struct phy_device *phydev)
40{
Philippe Schenker8c4506a2020-03-11 11:59:25 +010041 int tmp;
42
43 switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
44 case PHY_ID_KSZ9031:
45 /*
46 * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by
47 * default. The MAC and the layout don't add a skew between
48 * clock and data.
49 * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for
50 * the TXC path to get the required clock skews.
51 */
52 /* control data pad skew - devaddr = 0x02, register = 0x04 */
53 ksz9031_phy_extended_write(phydev, 0x02,
54 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
55 MII_KSZ9031_MOD_DATA_NO_POST_INC,
56 0x0070);
57 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
58 ksz9031_phy_extended_write(phydev, 0x02,
59 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
60 MII_KSZ9031_MOD_DATA_NO_POST_INC,
61 0x7777);
62 /* tx data pad skew - devaddr = 0x02, register = 0x06 */
63 ksz9031_phy_extended_write(phydev, 0x02,
64 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
65 MII_KSZ9031_MOD_DATA_NO_POST_INC,
66 0x0000);
67 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
68 ksz9031_phy_extended_write(phydev, 0x02,
69 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
70 MII_KSZ9031_MOD_DATA_NO_POST_INC,
71 0x03f4);
72 break;
73 case PHY_ID_KSZ9131:
74 default:
75 /* read rxc dll control - devaddr = 0x2, register = 0x4c */
76 tmp = ksz9031_phy_extended_read(phydev, 0x02,
77 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
78 MII_KSZ9031_MOD_DATA_NO_POST_INC);
79 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
80 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
81 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
82 tmp = ksz9031_phy_extended_write(phydev, 0x02,
83 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
84 MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
85 /* read txc dll control - devaddr = 0x02, register = 0x4d */
86 tmp = ksz9031_phy_extended_read(phydev, 0x02,
87 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
88 MII_KSZ9031_MOD_DATA_NO_POST_INC);
89 /* disable txdll bypass (enable 2ns skew delay on TXC) */
90 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
91 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
92 tmp = ksz9031_phy_extended_write(phydev, 0x02,
93 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
94 MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
95 break;
96 }
Igor Opaniuk309e65b2020-01-28 14:42:25 +010097
98 if (phydev->drv->config)
99 phydev->drv->config(phydev);
100 return 0;
101}
102#endif
103
104int board_init(void)
105{
106 if (IS_ENABLED(CONFIG_FEC_MXC))
107 setup_fec();
108
109 return 0;
110}
111
112int board_mmc_get_env_dev(int devno)
113{
114 return devno;
115}
116
117int board_late_init(void)
118{
119 return 0;
120}
121
122#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
123int ft_board_setup(void *blob, bd_t *bd)
124{
125 return 0;
126}
127#endif