| Łukasz Dałek | bbebc4d | 2012-08-19 00:21:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * PXA25x UDC definitions |
| 3 | * |
| 4 | * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com> |
| 5 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| Łukasz Dałek | bbebc4d | 2012-08-19 00:21:02 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __REGS_USB_H__ |
| 10 | #define __REGS_USB_H__ |
| 11 | |
| 12 | struct pxa25x_udc_regs { |
| 13 | /* UDC Control Register */ |
| 14 | uint32_t udccr; /* 0x000 */ |
| 15 | uint32_t reserved1; |
| 16 | |
| 17 | /* UDC Control Function Register */ |
| 18 | uint32_t udccfr; /* 0x008 */ |
| 19 | uint32_t reserved2; |
| 20 | |
| 21 | /* UDC Endpoint Control/Status Registers */ |
| 22 | uint32_t udccs[16]; /* 0x010 - 0x04c */ |
| 23 | |
| 24 | /* UDC Interrupt Control/Status Registers */ |
| 25 | uint32_t uicr0; /* 0x050 */ |
| 26 | uint32_t uicr1; /* 0x054 */ |
| 27 | uint32_t usir0; /* 0x058 */ |
| 28 | uint32_t usir1; /* 0x05c */ |
| 29 | |
| 30 | /* UDC Frame Number/Byte Count Registers */ |
| 31 | uint32_t ufnrh; /* 0x060 */ |
| 32 | uint32_t ufnrl; /* 0x064 */ |
| 33 | uint32_t ubcr2; /* 0x068 */ |
| 34 | uint32_t ubcr4; /* 0x06c */ |
| 35 | uint32_t ubcr7; /* 0x070 */ |
| 36 | uint32_t ubcr9; /* 0x074 */ |
| 37 | uint32_t ubcr12; /* 0x078 */ |
| 38 | uint32_t ubcr14; /* 0x07c */ |
| 39 | |
| 40 | /* UDC Endpoint Data Registers */ |
| 41 | uint32_t uddr0; /* 0x080 */ |
| 42 | uint32_t reserved3[7]; |
| 43 | uint32_t uddr5; /* 0x0a0 */ |
| 44 | uint32_t reserved4[7]; |
| 45 | uint32_t uddr10; /* 0x0c0 */ |
| 46 | uint32_t reserved5[7]; |
| 47 | uint32_t uddr15; /* 0x0e0 */ |
| 48 | uint32_t reserved6[7]; |
| 49 | uint32_t uddr1; /* 0x100 */ |
| 50 | uint32_t reserved7[31]; |
| 51 | uint32_t uddr2; /* 0x180 */ |
| 52 | uint32_t reserved8[31]; |
| 53 | uint32_t uddr3; /* 0x200 */ |
| 54 | uint32_t reserved9[127]; |
| 55 | uint32_t uddr4; /* 0x400 */ |
| 56 | uint32_t reserved10[127]; |
| 57 | uint32_t uddr6; /* 0x600 */ |
| 58 | uint32_t reserved11[31]; |
| 59 | uint32_t uddr7; /* 0x680 */ |
| 60 | uint32_t reserved12[31]; |
| 61 | uint32_t uddr8; /* 0x700 */ |
| 62 | uint32_t reserved13[127]; |
| 63 | uint32_t uddr9; /* 0x900 */ |
| 64 | uint32_t reserved14[127]; |
| 65 | uint32_t uddr11; /* 0xb00 */ |
| 66 | uint32_t reserved15[31]; |
| 67 | uint32_t uddr12; /* 0xb80 */ |
| 68 | uint32_t reserved16[31]; |
| 69 | uint32_t uddr13; /* 0xc00 */ |
| 70 | uint32_t reserved17[127]; |
| 71 | uint32_t uddr14; /* 0xe00 */ |
| 72 | |
| 73 | }; |
| 74 | |
| 75 | #define PXA25X_UDC_BASE 0x40600000 |
| 76 | |
| 77 | #define UDCCR_UDE (1 << 0) |
| 78 | #define UDCCR_UDA (1 << 1) |
| 79 | #define UDCCR_RSM (1 << 2) |
| 80 | #define UDCCR_RESIR (1 << 3) |
| 81 | #define UDCCR_SUSIR (1 << 4) |
| 82 | #define UDCCR_SRM (1 << 5) |
| 83 | #define UDCCR_RSTIR (1 << 6) |
| 84 | #define UDCCR_REM (1 << 7) |
| 85 | |
| 86 | /* Bulk IN endpoint 1/6/11 */ |
| 87 | #define UDCCS_BI_TSP (1 << 7) |
| 88 | #define UDCCS_BI_FST (1 << 5) |
| 89 | #define UDCCS_BI_SST (1 << 4) |
| 90 | #define UDCCS_BI_TUR (1 << 3) |
| 91 | #define UDCCS_BI_FTF (1 << 2) |
| 92 | #define UDCCS_BI_TPC (1 << 1) |
| 93 | #define UDCCS_BI_TFS (1 << 0) |
| 94 | |
| 95 | /* Bulk OUT endpoint 2/7/12 */ |
| 96 | #define UDCCS_BO_RSP (1 << 7) |
| 97 | #define UDCCS_BO_RNE (1 << 6) |
| 98 | #define UDCCS_BO_FST (1 << 5) |
| 99 | #define UDCCS_BO_SST (1 << 4) |
| 100 | #define UDCCS_BO_DME (1 << 3) |
| 101 | #define UDCCS_BO_RPC (1 << 1) |
| 102 | #define UDCCS_BO_RFS (1 << 0) |
| 103 | |
| 104 | /* Isochronous OUT endpoint 4/9/14 */ |
| 105 | #define UDCCS_IO_RSP (1 << 7) |
| 106 | #define UDCCS_IO_RNE (1 << 6) |
| 107 | #define UDCCS_IO_DME (1 << 3) |
| 108 | #define UDCCS_IO_ROF (1 << 2) |
| 109 | #define UDCCS_IO_RPC (1 << 1) |
| 110 | #define UDCCS_IO_RFS (1 << 0) |
| 111 | |
| 112 | /* Control endpoint 0 */ |
| 113 | #define UDCCS0_OPR (1 << 0) |
| 114 | #define UDCCS0_IPR (1 << 1) |
| 115 | #define UDCCS0_FTF (1 << 2) |
| 116 | #define UDCCS0_DRWF (1 << 3) |
| 117 | #define UDCCS0_SST (1 << 4) |
| 118 | #define UDCCS0_FST (1 << 5) |
| 119 | #define UDCCS0_RNE (1 << 6) |
| 120 | #define UDCCS0_SA (1 << 7) |
| 121 | |
| 122 | #define UICR0_IM0 (1 << 0) |
| 123 | |
| 124 | #define USIR0_IR0 (1 << 0) |
| 125 | #define USIR0_IR1 (1 << 1) |
| 126 | #define USIR0_IR2 (1 << 2) |
| 127 | #define USIR0_IR3 (1 << 3) |
| 128 | #define USIR0_IR4 (1 << 4) |
| 129 | #define USIR0_IR5 (1 << 5) |
| 130 | #define USIR0_IR6 (1 << 6) |
| 131 | #define USIR0_IR7 (1 << 7) |
| 132 | |
| 133 | #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ |
| 134 | #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ |
| 135 | /* |
| 136 | * Intel(R) PXA255 Processor Specification, September 2003 (page 31) |
| 137 | * define new "must be one" bits in UDCCFR (see Table 12-13.) |
| 138 | */ |
| 139 | #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) |
| 140 | |
| 141 | #define UFNRH_SIR (1 << 7) /* SOF interrupt request */ |
| 142 | #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ |
| 143 | #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ |
| 144 | #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ |
| 145 | #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ |
| 146 | |
| 147 | #endif /* __REGS_USB_H__ */ |