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git01.mediatek.com / filogic / uboot / 68e60eb84a57a25d98824dba96f641eb8b6c82ea / . / arch / m68k / include / asm / immap_5301x.h
blob: 87ac770cf87ca9af1f240e05042b19d95def4e31 [file] [log] [blame]
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]1/*
2 * MCF5301x Internal Memory Map
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __IMMAP_5301X__
27#define __IMMAP_5301X__
28
29#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
30#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
31#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
32#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000)
33#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
34#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000)
35#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
36#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
37#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
38#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
39#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
40#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
41#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
42#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
43#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
44#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
45#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
46#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
47#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
48#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
49#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
50#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
51#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000)
52#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000)
53#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000)
54#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000)
55#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000)
56#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
57#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
58#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
59#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000)
60#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000)
61#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000)
62#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000)
63#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
64#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
65#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
66#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000)
67#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000)
68#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000)
69
70#include <asm/coldfire/crossbar.h>
71#include <asm/coldfire/dspi.h>
72#include <asm/coldfire/edma.h>
73#include <asm/coldfire/eport.h>
74#include <asm/coldfire/flexbus.h>
75#include <asm/coldfire/intctrl.h>
76#include <asm/coldfire/ssi.h>
77#include <asm/coldfire/rng.h>
78#include <asm/rtc.h>
79
80/* System Controller Module */
81typedef struct scm1 {
82 u32 mpr; /* 0x00 Master Privilege */
83 u32 rsvd1[7];
84 u32 pacra; /* 0x20 Peripheral Access Ctrl A */
85 u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
86 u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
87 u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
88 u32 rsvd2[4];
89 u32 pacre; /* 0x40 Peripheral Access Ctrl E */
90 u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
91 u32 pacrg; /* 0x48 Peripheral Access Ctrl G */
92} scm1_t;
93
94typedef struct scm2 {
95 u8 rsvd1[19]; /* 0x00 - 0x12 */
96 u8 wcr; /* 0x13 */
97 u16 rsvd2; /* 0x14 - 0x15 */
98 u16 cwcr; /* 0x16 */
99 u8 rsvd3[3]; /* 0x18 - 0x1A */
100 u8 cwsr; /* 0x1B */
101 u8 rsvd4[3]; /* 0x1C - 0x1E */
102 u8 scmisr; /* 0x1F */
103 u32 rsvd5; /* 0x20 - 0x23 */
104 u8 bcr; /* 0x24 */
105 u8 rsvd6[74]; /* 0x25 - 0x6F */
106 u32 cfadr; /* 0x70 */
107 u8 rsvd7; /* 0x74 */
108 u8 cfier; /* 0x75 */
109 u8 cfloc; /* 0x76 */
110 u8 cfatr; /* 0x77 */
111 u32 rsvd8; /* 0x78 - 0x7B */
112 u32 cfdtr; /* 0x7C */
113} scm2_t;
114
115/* PWM module */
116typedef struct pwm_ctrl {
117 u8 en; /* 0x00 PWM Enable */
118 u8 pol; /* 0x01 Polarity */
119 u8 clk; /* 0x02 Clock Select */
120 u8 prclk; /* 0x03 Prescale Clock Select */
121 u8 cae; /* 0x04 Center Align Enable */
122 u8 ctl; /* 0x05 Ctrl */
123 u8 res1[2]; /* 0x06 - 0x07 */
124 u8 scla; /* 0x08 Scale A */
125 u8 sclb; /* 0x09 Scale B */
126 u8 res2[2]; /* 0x0A - 0x0B */
127 u8 cnt0; /* 0x0C Channel 0 Counter */
128 u8 cnt1; /* 0x0D Channel 1 Counter */
129 u8 cnt2; /* 0x0E Channel 2 Counter */
130 u8 cnt3; /* 0x0F Channel 3 Counter */
131 u8 cnt4; /* 0x10 Channel 4 Counter */
132 u8 cnt5; /* 0x11 Channel 5 Counter */
133 u8 cnt6; /* 0x12 Channel 6 Counter */
134 u8 cnt7; /* 0x13 Channel 7 Counter */
135 u8 per0; /* 0x14 Channel 0 Period */
136 u8 per1; /* 0x15 Channel 1 Period */
137 u8 per2; /* 0x16 Channel 2 Period */
138 u8 per3; /* 0x17 Channel 3 Period */
139 u8 per4; /* 0x18 Channel 4 Period */
140 u8 per5; /* 0x19 Channel 5 Period */
141 u8 per6; /* 0x1A Channel 6 Period */
142 u8 per7; /* 0x1B Channel 7 Period */
143 u8 dty0; /* 0x1C Channel 0 Duty */
144 u8 dty1; /* 0x1D Channel 1 Duty */
145 u8 dty2; /* 0x1E Channel 2 Duty */
146 u8 dty3; /* 0x1F Channel 3 Duty */
147 u8 dty4; /* 0x20 Channel 4 Duty */
148 u8 dty5; /* 0x21 Channel 5 Duty */
149 u8 dty6; /* 0x22 Channel 6 Duty */
150 u8 dty7; /* 0x23 Channel 7 Duty */
151 u8 sdn; /* 0x24 Shutdown */
152 u8 res3[3]; /* 0x25 - 0x27 */
153} pwm_t;
154
155/* Chip configuration module */
156typedef struct rcm {
157 u8 rcr;
158 u8 rsr;
159} rcm_t;
160
161typedef struct ccm_ctrl {
162 u16 ccr; /* 0x00 Chip Cfg */
163 u16 res1; /* 0x02 */
164 u16 rcon; /* 0x04 Reset Cfg */
165 u16 cir; /* 0x06 Chip ID */
166 u32 res2; /* 0x08 */
167 u16 misccr; /* 0x0A Misc Ctrl */
168 u16 cdr; /* 0x0C Clock divider */
169 u16 uhcsr; /* 0x10 USB Host status */
170 u16 uocsr; /* 0x12 USB On-the-Go Status */
171 u16 res3; /* 0x14 */
172 u16 codeccr; /* 0x16 Codec Control */
173 u16 misccr2; /* 0x18 Misc2 Ctrl */
174} ccm_t;
175
176/* GPIO port */
177typedef struct gpio_ctrl {
178 /* Port Output Data */
179 u8 podr_fbctl; /* 0x00 */
180 u8 podr_be; /* 0x01 */
181 u8 podr_cs; /* 0x02 */
182 u8 podr_dspi; /* 0x03 */
183 u8 res01; /* 0x04 */
184 u8 podr_fec0; /* 0x05 */
185 u8 podr_feci2c; /* 0x06 */
186 u8 res02[2]; /* 0x07 - 0x08 */
187 u8 podr_simp1; /* 0x09 */
188 u8 podr_simp0; /* 0x0A */
189 u8 podr_timer; /* 0x0B */
190 u8 podr_uart; /* 0x0C */
191 u8 podr_debug; /* 0x0D */
192 u8 res03; /* 0x0E */
193 u8 podr_sdhc; /* 0x0F */
194 u8 podr_ssi; /* 0x10 */
195 u8 res04[3]; /* 0x11 - 0x13 */
196
197 /* Port Data Direction */
198 u8 pddr_fbctl; /* 0x14 */
199 u8 pddr_be; /* 0x15 */
200 u8 pddr_cs; /* 0x16 */
201 u8 pddr_dspi; /* 0x17 */
202 u8 res05; /* 0x18 */
203 u8 pddr_fec0; /* 0x19 */
204 u8 pddr_feci2c; /* 0x1A */
205 u8 res06[2]; /* 0x1B - 0x1C */
206 u8 pddr_simp1; /* 0x1D */
207 u8 pddr_simp0; /* 0x1E */
208 u8 pddr_timer; /* 0x1F */
209 u8 pddr_uart; /* 0x20 */
210 u8 pddr_debug; /* 0x21 */
211 u8 res07; /* 0x22 */
212 u8 pddr_sdhc; /* 0x23 */
213 u8 pddr_ssi; /* 0x24 */
214 u8 res08[3]; /* 0x25 - 0x27 */
215
216 /* Port Data Direction */
217 u8 ppdr_fbctl; /* 0x28 */
218 u8 ppdr_be; /* 0x29 */
219 u8 ppdr_cs; /* 0x2A */
220 u8 ppdr_dspi; /* 0x2B */
221 u8 res09; /* 0x2C */
222 u8 ppdr_fec0; /* 0x2D */
223 u8 ppdr_feci2c; /* 0x2E */
224 u8 res10[2]; /* 0x2F - 0x30 */
225 u8 ppdr_simp1; /* 0x31 */
226 u8 ppdr_simp0; /* 0x32 */
227 u8 ppdr_timer; /* 0x33 */
228 u8 ppdr_uart; /* 0x34 */
229 u8 ppdr_debug; /* 0x35 */
230 u8 res11; /* 0x36 */
231 u8 ppdr_sdhc; /* 0x37 */
232 u8 ppdr_ssi; /* 0x38 */
233 u8 res12[3]; /* 0x39 - 0x3B */
234
235 /* Port Clear Output Data */
236 u8 pclrr_fbctl; /* 0x3C */
237 u8 pclrr_be; /* 0x3D */
238 u8 pclrr_cs; /* 0x3E */
239 u8 pclrr_dspi; /* 0x3F */
240 u8 res13; /* 0x40 */
241 u8 pclrr_fec0; /* 0x41 */
242 u8 pclrr_feci2c; /* 0x42 */
243 u8 res14[2]; /* 0x43 - 0x44 */
244 u8 pclrr_simp1; /* 0x45 */
245 u8 pclrr_simp0; /* 0x46 */
246 u8 pclrr_timer; /* 0x47 */
247 u8 pclrr_uart; /* 0x48 */
248 u8 pclrr_debug; /* 0x49 */
249 u8 res15; /* 0x4A */
250 u8 pclrr_sdhc; /* 0x4B */
251 u8 pclrr_ssi; /* 0x4C */
252 u8 res16[3]; /* 0x4D - 0x4F */
253
254 /* Pin Assignment */
255 u8 par_fbctl; /* 0x50 */
256 u8 par_be; /* 0x51 */
257 u8 par_cs; /* 0x52 */
258 u8 res17; /* 0x53 */
259 u8 par_dspih; /* 0x54 */
260 u8 par_dspil; /* 0x55 */
261 u8 par_fec; /* 0x56 */
262 u8 par_feci2c; /* 0x57 */
263 u8 par_irq0h; /* 0x58 */
264 u8 par_irq0l; /* 0x59 */
265 u8 par_irq1h; /* 0x5A */
266 u8 par_irq1l; /* 0x5B */
267 u8 par_simp1h; /* 0x5C */
268 u8 par_simp1l; /* 0x5D */
269 u8 par_simp0; /* 0x5E */
270 u8 par_timer; /* 0x5F */
271 u8 par_uart; /* 0x60 */
272 u8 res18; /* 0x61 */
273 u8 par_debug; /* 0x62 */
274 u8 par_sdhc; /* 0x63 */
275 u8 par_ssih; /* 0x64 */
276 u8 par_ssil; /* 0x65 */
277 u8 res19[2]; /* 0x66 - 0x67 */
278
279 /* Mode Select Control */
280 /* Drive Strength Control */
281 u8 mscr_mscr1; /* 0x68 */
282 u8 mscr_mscr2; /* 0x69 */
283 u8 mscr_mscr3; /* 0x6A */
284 u8 mscr_mscr45; /* 0x6B */
285 u8 srcr_dspi; /* 0x6C */
286 u8 dscr_fec; /* 0x6D */
287 u8 srcr_i2c; /* 0x6E */
288 u8 srcr_irq; /* 0x6F */
289
290 u8 srcr_sim; /* 0x70 */
291 u8 srcr_timer; /* 0x71 */
292 u8 srcr_uart; /* 0x72 */
293 u8 res20; /* 0x73 */
294 u8 srcr_sdhc; /* 0x74 */
295 u8 srcr_ssi; /* 0x75 */
296 u8 res21[2]; /* 0x76 - 0x77 */
297 u8 pcr_pcrh; /* 0x78 */
298 u8 pcr_pcrl; /* 0x79 */
299} gpio_t;
300
301/* SDRAM controller */
302typedef struct sdram_ctrl {
303 u32 mode; /* 0x00 Mode/Extended Mode */
304 u32 ctrl; /* 0x04 Ctrl */
305 u32 cfg1; /* 0x08 Cfg 1 */
306 u32 cfg2; /* 0x0C Cfg 2 */
307 u32 res1[64]; /* 0x10 - 0x10F */
308 u32 cs0; /* 0x110 Chip Select 0 Cfg */
309 u32 cs1; /* 0x114 Chip Select 1 Cfg */
310} sdram_t;
311
312/* Clock Module */
313typedef struct pll_ctrl {
314 u32 pcr; /* 0x00 Ctrl */
315 u32 pdr; /* 0x04 Divider */
316 u32 psr; /* 0x08 Status */
317} pll_t;
318
319typedef struct rtcex {
320 u32 rsvd1[3];
321 u32 gocu;
322 u32 gocl;
323} rtcex_t;
324#endif /* __IMMAP_5301X__ */