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git01.mediatek.com / filogic / uboot / 68e382b85047dbe54859ea448710dc573330b0bf / . / arch / arm / include / asm / arch-am33xx / cpu.h
blob: d18750adac6fd9f9c6a718daa020ddf9cdae39fb [file] [log] [blame]
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]1/*
2 * cpu.h
3 *
4 * AM33xx specific header file
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef _AM33XX_CPU_H
20#define _AM33XX_CPU_H
21
22#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
23#include <asm/types.h>
24#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
25
26#include <asm/arch/hardware.h>
27
28#define BIT(x) (1 << x)
29#define CL_BIT(x) (0 << x)
30
31/* Timer register bits */
32#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
33#define TCLR_AR BIT(1) /* Auto reload */
34#define TCLR_PRE BIT(5) /* Pre-scaler enable */
35#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
36#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
37
38/* device type */
39#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
40#define TST_DEVICE 0x0
41#define EMU_DEVICE 0x1
42#define HS_DEVICE 0x2
43#define GP_DEVICE 0x3
44
45/* cpu-id for AM33XX family */
46#define AM335X 0xB944
47#define DEVICE_ID 0x44E10600
48
49/* This gives the status of the boot mode pins on the evm */
50#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
51 | BIT(3) | BIT(4))
52
53/* Reset control */
Chandan Nath68e382b2012-01-09 20:38:55 +0000[diff] [blame^]54#ifdef CONFIG_AM33XX
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]55#define PRM_RSTCTRL 0x44E00F00
56#endif
57#define PRM_RSTCTRL_RESET 0x01
58
59#ifndef __KERNEL_STRICT_NAMES
60#ifndef __ASSEMBLY__
61/* Encapsulating core pll registers */
62struct cm_wkuppll {
63 unsigned int wkclkstctrl; /* offset 0x00 */
64 unsigned int wkctrlclkctrl; /* offset 0x04 */
65 unsigned int resv1[1];
66 unsigned int wkl4wkclkctrl; /* offset 0x0c */
67 unsigned int resv2[4];
68 unsigned int idlestdpllmpu; /* offset 0x20 */
69 unsigned int resv3[2];
70 unsigned int clkseldpllmpu; /* offset 0x2c */
71 unsigned int resv4[1];
72 unsigned int idlestdpllddr; /* offset 0x34 */
73 unsigned int resv5[2];
74 unsigned int clkseldpllddr; /* offset 0x40 */
75 unsigned int resv6[4];
76 unsigned int clkseldplldisp; /* offset 0x54 */
77 unsigned int resv7[1];
78 unsigned int idlestdpllcore; /* offset 0x5c */
79 unsigned int resv8[2];
80 unsigned int clkseldpllcore; /* offset 0x68 */
81 unsigned int resv9[1];
82 unsigned int idlestdpllper; /* offset 0x70 */
83 unsigned int resv10[3];
84 unsigned int divm4dpllcore; /* offset 0x80 */
85 unsigned int divm5dpllcore; /* offset 0x84 */
86 unsigned int clkmoddpllmpu; /* offset 0x88 */
87 unsigned int clkmoddpllper; /* offset 0x8c */
88 unsigned int clkmoddpllcore; /* offset 0x90 */
89 unsigned int clkmoddpllddr; /* offset 0x94 */
90 unsigned int clkmoddplldisp; /* offset 0x98 */
91 unsigned int clkseldpllper; /* offset 0x9c */
92 unsigned int divm2dpllddr; /* offset 0xA0 */
93 unsigned int divm2dplldisp; /* offset 0xA4 */
94 unsigned int divm2dpllmpu; /* offset 0xA8 */
95 unsigned int divm2dpllper; /* offset 0xAC */
96 unsigned int resv11[1];
97 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
98 unsigned int resv12[8];
99 unsigned int divm6dpllcore; /* offset 0xD8 */
100};
101
102/**
103 * Encapsulating peripheral functional clocks
104 * pll registers
105 */
106struct cm_perpll {
107 unsigned int l4lsclkstctrl; /* offset 0x00 */
108 unsigned int l3sclkstctrl; /* offset 0x04 */
109 unsigned int l4fwclkstctrl; /* offset 0x08 */
110 unsigned int l3clkstctrl; /* offset 0x0c */
111 unsigned int resv1[6];
112 unsigned int emifclkctrl; /* offset 0x28 */
113 unsigned int ocmcramclkctrl; /* offset 0x2c */
114 unsigned int resv2[12];
115 unsigned int l4lsclkctrl; /* offset 0x60 */
116 unsigned int l4fwclkctrl; /* offset 0x64 */
117 unsigned int resv3[6];
118 unsigned int timer2clkctrl; /* offset 0x80 */
119 unsigned int resv4[19];
120 unsigned int emiffwclkctrl; /* offset 0xD0 */
121 unsigned int resv5[2];
122 unsigned int l3instrclkctrl; /* offset 0xDC */
123 unsigned int l3clkctrl; /* Offset 0xE0 */
124 unsigned int resv6[14];
125 unsigned int l4hsclkstctrl; /* offset 0x11C */
126 unsigned int l4hsclkctrl; /* offset 0x120 */
127};
128
129/* Encapsulating Display pll registers */
130struct cm_dpll {
131 unsigned int resv1[2];
132 unsigned int clktimer2clk; /* offset 0x08 */
133};
134
135/* Watchdog timer registers */
136struct wd_timer {
137 unsigned int resv1[4];
138 unsigned int wdtwdsc; /* offset 0x010 */
139 unsigned int wdtwdst; /* offset 0x014 */
140 unsigned int wdtwisr; /* offset 0x018 */
141 unsigned int wdtwier; /* offset 0x01C */
142 unsigned int wdtwwer; /* offset 0x020 */
143 unsigned int wdtwclr; /* offset 0x024 */
144 unsigned int wdtwcrr; /* offset 0x028 */
145 unsigned int wdtwldr; /* offset 0x02C */
146 unsigned int wdtwtgr; /* offset 0x030 */
147 unsigned int wdtwwps; /* offset 0x034 */
148 unsigned int resv2[3];
149 unsigned int wdtwdly; /* offset 0x044 */
150 unsigned int wdtwspr; /* offset 0x048 */
151 unsigned int resv3[1];
152 unsigned int wdtwqeoi; /* offset 0x050 */
153 unsigned int wdtwqstar; /* offset 0x054 */
154 unsigned int wdtwqsta; /* offset 0x058 */
155 unsigned int wdtwqens; /* offset 0x05C */
156 unsigned int wdtwqenc; /* offset 0x060 */
157 unsigned int resv4[39];
158 unsigned int wdt_unfr; /* offset 0x100 */
159};
160
161/* Timer Registers */
162struct timer_reg {
163 unsigned int resv1[4];
164 unsigned int tiocpcfgreg; /* offset 0x10 */
165 unsigned int resv2[9];
166 unsigned int tclrreg; /* offset 0x38 */
167 unsigned int tcrrreg; /* offset 0x3C */
168 unsigned int tldrreg; /* offset 0x40 */
169 unsigned int resv3[4];
170 unsigned int tsicrreg; /* offset 0x54 */
171};
172
173/* Timer 32 bit registers */
174struct gptimer {
175 unsigned int tidr; /* offset 0x00 */
176 unsigned int res1[0xc];
177 unsigned int tiocp_cfg; /* offset 0x10 */
178 unsigned int res2[0xc];
179 unsigned int tier; /* offset 0x20 */
180 unsigned int tistatr; /* offset 0x24 */
181 unsigned int tistat; /* offset 0x28 */
182 unsigned int tisr; /* offset 0x2c */
183 unsigned int tcicr; /* offset 0x30 */
184 unsigned int twer; /* offset 0x34 */
185 unsigned int tclr; /* offset 0x38 */
186 unsigned int tcrr; /* offset 0x3c */
187 unsigned int tldr; /* offset 0x40 */
188 unsigned int ttgr; /* offset 0x44 */
189 unsigned int twpc; /* offset 0x48 */
190 unsigned int tmar; /* offset 0x4c */
191 unsigned int tcar1; /* offset 0x50 */
192 unsigned int tscir; /* offset 0x54 */
193 unsigned int tcar2; /* offset 0x58 */
194};
195
196/* UART Registers */
197struct uart_sys {
198 unsigned int resv1[21];
199 unsigned int uartsyscfg; /* offset 0x54 */
200 unsigned int uartsyssts; /* offset 0x58 */
201};
202
203/* VTP Registers */
204struct vtp_reg {
205 unsigned int vtp0ctrlreg;
206};
207
208/* Control Status Register */
209struct ctrl_stat {
210 unsigned int resv1[16];
211 unsigned int statusreg; /* ofset 0x40 */
212};
213
214void init_timer(void);
215#endif /* __ASSEMBLY__ */
216#endif /* __KERNEL_STRICT_NAMES */
217
218#endif /* _AM33XX_CPU_H */