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git01.mediatek.com / filogic / uboot / 68b6dba2dfb2789bc6d4047c33c6cbccf9b63592 / . / arch / x86 / cpu / u-boot.lds
blob: a31f4220a0008547d8e1e44e713130ba9642381b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]2/*
3 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]4 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]5 */
6
Graeme Russc5881f12011-04-13 19:43:25 +1000[diff] [blame]7#include <config.h>
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]8OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
9OUTPUT_ARCH(i386)
10ENTRY(_start)
11
12SECTIONS
13{
Simon Glass3e2c91c2016-03-13 19:07:29 -0600[diff] [blame]14#ifndef CONFIG_CMDLINE
Andrew Scull5a9095c2022-05-30 10:00:04 +0000[diff] [blame]15 /DISCARD/ : { *(__u_boot_list_2_cmd_*) }
Simon Glass3e2c91c2016-03-13 19:07:29 -0600[diff] [blame]16#endif
17
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]18 . = CONFIG_TEXT_BASE; /* Location of bootcode in flash */
Graeme Russae428db2010-10-07 20:03:31 +1100[diff] [blame]19 __text_start = .;
Alexander Graf94a10f22018-06-12 07:48:37 +0200[diff] [blame]20
21 .text.start : { *(.text.start); }
22
23 .__efi_runtime_start : {
24 *(.__efi_runtime_start)
25 }
26
27 .efi_runtime : {
28 *(.text.efi_runtime*)
29 *(.rodata.efi_runtime*)
30 *(.data.efi_runtime*)
31 }
32
33 .__efi_runtime_stop : {
34 *(.__efi_runtime_stop)
35 }
36
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]37 .text : { *(.text*); }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]38
39 . = ALIGN(4);
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]40
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]41 . = ALIGN(4);
Andrew Scull5a9095c2022-05-30 10:00:04 +0000[diff] [blame]42 __u_boot_list : {
43 KEEP(*(SORT(__u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]44 }
45
46 . = ALIGN(4);
Simon Glasscdfe6962016-09-25 15:27:35 -0600[diff] [blame]47 .rodata : {
48 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
49 KEEP(*(.rodata.efi.init));
50 }
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]51
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]52 . = ALIGN(4);
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]53 .data : { *(.data*) }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]54
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]55 . = ALIGN(4);
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]56 .hash : { *(.hash*) }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]57
58 . = ALIGN(4);
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]59 .got : { *(.got*) }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]60
61 . = ALIGN(4);
Simon Glasscdfe6962016-09-25 15:27:35 -0600[diff] [blame]62
Simon Glasscdfe6962016-09-25 15:27:35 -0600[diff] [blame]63 .efi_runtime_rel_start :
64 {
65 *(.__efi_runtime_rel_start)
66 }
67
68 .efi_runtime_rel : {
Alexander Graf94a10f22018-06-12 07:48:37 +0200[diff] [blame]69 *(.rel*.efi_runtime)
70 *(.rel*.efi_runtime.*)
Simon Glasscdfe6962016-09-25 15:27:35 -0600[diff] [blame]71 }
72
73 .efi_runtime_rel_stop :
74 {
75 *(.__efi_runtime_rel_stop)
76 }
77
78 . = ALIGN(4);
79
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]80 __data_end = .;
Simon Glass3e93e332013-03-05 14:39:54 +0000[diff] [blame]81 __init_end = .;
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]82
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]83 . = ALIGN(4);
Simon Glass18cc2bc2013-02-28 19:26:14 +0000[diff] [blame]84 .dynsym : { *(.dynsym*) }
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]85
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]86 . = ALIGN(4);
Graeme Russae428db2010-10-07 20:03:31 +1100[diff] [blame]87 __rel_dyn_start = .;
Simon Glass1eb8ebc2014-11-14 18:18:24 -0700[diff] [blame]88 .rel.dyn : {
89 *(.rel*)
90 }
Graeme Russae428db2010-10-07 20:03:31 +1100[diff] [blame]91 __rel_dyn_end = .;
Simon Glass781db8c2013-02-28 19:26:13 +0000[diff] [blame]92 . = ALIGN(4);
93 _end = .;
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]94
Simon Glass18cc2bc2013-02-28 19:26:14 +0000[diff] [blame]95 .bss __rel_dyn_start (OVERLAY) : {
96 __bss_start = .;
Alexander Graf61c76782018-08-20 14:17:41 +0200[diff] [blame]97 *(.bss*)
Simon Glass18cc2bc2013-02-28 19:26:14 +0000[diff] [blame]98 *(COM*)
99 . = ALIGN(4);
100 __bss_end = .;
101 }
102
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]103 /DISCARD/ : { *(.dynstr*) }
104 /DISCARD/ : { *(.dynamic*) }
105 /DISCARD/ : { *(.plt*) }
106 /DISCARD/ : { *(.interp*) }
107 /DISCARD/ : { *(.gnu*) }
Bin Meng3eb15f52021-06-18 15:09:30 +0800[diff] [blame]108 /DISCARD/ : { *(.note.gnu.property) }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]109
Simon Glass706f6f52017-01-16 07:03:45 -0700[diff] [blame]110#ifdef CONFIG_X86_16BIT_INIT
Graeme Russ3fe48602011-02-12 15:11:24 +1100[diff] [blame]111 /*
112 * The following expressions place the 16-bit Real-Mode code and
113 * Reset Vector at the end of the Flash ROM
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]114 */
Simon Glass20ec2532014-11-14 18:18:25 -0700[diff] [blame]115 . = START_16 - RESET_SEG_START;
116 .start16 : AT (START_16) {
117 KEEP(*(.start16));
118 }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]119
Simon Glass20ec2532014-11-14 18:18:25 -0700[diff] [blame]120 . = RESET_VEC_LOC - RESET_SEG_START;
121 .resetvec : AT (RESET_VEC_LOC) {
122 KEEP(*(.resetvec));
123 }
Gabe Black14f82462012-11-27 21:08:06 +0000[diff] [blame]124#endif
Simon Glass20ec2532014-11-14 18:18:25 -0700[diff] [blame]125
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]126}