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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chin Liang Seecca9f452013-12-30 18:26:14 -06002/*
3 * (C) Copyright 2013 Altera Corporation <www.altera.com>
Chin Liang Seecca9f452013-12-30 18:26:14 -06004 */
5
6#include <common.h>
Chin Liang Seecca9f452013-12-30 18:26:14 -06007#include <asm/arch/clock_manager.h>
8#include <asm/arch/system_manager.h>
Marek Vasut26608602018-08-01 18:28:35 +02009#include <clk.h>
Marek Vasutae66f3c2015-11-30 20:41:04 +010010#include <dm.h>
11#include <dwmmc.h>
12#include <errno.h>
13#include <fdtdec.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <dm/device_compat.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090015#include <linux/libfdt.h>
Marek Vasutae66f3c2015-11-30 20:41:04 +010016#include <linux/err.h>
17#include <malloc.h>
Ley Foon Tan5a694d02018-06-14 18:45:21 +080018#include <reset.h>
Marek Vasutae66f3c2015-11-30 20:41:04 +010019
20DECLARE_GLOBAL_DATA_PTR;
Chin Liang Seecca9f452013-12-30 18:26:14 -060021
Simon Glassa3a43202016-07-05 17:10:16 -060022struct socfpga_dwmci_plat {
23 struct mmc_config cfg;
24 struct mmc mmc;
25};
26
Marek Vasutae66f3c2015-11-30 20:41:04 +010027/* socfpga implmentation specific driver private data */
Chin Liang See48e7bf92015-11-26 09:43:43 +080028struct dwmci_socfpga_priv_data {
Marek Vasutae66f3c2015-11-30 20:41:04 +010029 struct dwmci_host host;
30 unsigned int drvsel;
31 unsigned int smplsel;
Chin Liang See48e7bf92015-11-26 09:43:43 +080032};
33
Ley Foon Tan5a694d02018-06-14 18:45:21 +080034static void socfpga_dwmci_reset(struct udevice *dev)
35{
36 struct reset_ctl_bulk reset_bulk;
37 int ret;
38
39 ret = reset_get_bulk(dev, &reset_bulk);
40 if (ret) {
41 dev_warn(dev, "Can't get reset: %d\n", ret);
42 return;
43 }
44
45 reset_deassert_bulk(&reset_bulk);
46}
47
Chin Liang See48e7bf92015-11-26 09:43:43 +080048static void socfpga_dwmci_clksel(struct dwmci_host *host)
49{
50 struct dwmci_socfpga_priv_data *priv = host->priv;
Dinh Nguyenc4b66c42015-12-02 13:31:33 -060051 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
52 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
Chin Liang Seecca9f452013-12-30 18:26:14 -060053
54 /* Disable SDMMC clock. */
Ley Foon Tan26695912019-11-08 10:38:21 +080055 clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
56 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
Chin Liang Seecca9f452013-12-30 18:26:14 -060057
Chin Liang See48e7bf92015-11-26 09:43:43 +080058 debug("%s: drvsel %d smplsel %d\n", __func__,
59 priv->drvsel, priv->smplsel);
Ley Foon Tan3d3a8602019-11-08 10:38:20 +080060 writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
Chin Liang Seecca9f452013-12-30 18:26:14 -060061
62 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
Ley Foon Tan3d3a8602019-11-08 10:38:20 +080063 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
Chin Liang Seecca9f452013-12-30 18:26:14 -060064
65 /* Enable SDMMC clock */
Ley Foon Tan26695912019-11-08 10:38:21 +080066 setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
67 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
Chin Liang Seecca9f452013-12-30 18:26:14 -060068}
69
Marek Vasut26608602018-08-01 18:28:35 +020070static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
Chin Liang Seecca9f452013-12-30 18:26:14 -060071{
Marek Vasutae66f3c2015-11-30 20:41:04 +010072 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
73 struct dwmci_host *host = &priv->host;
Marek Vasut26608602018-08-01 18:28:35 +020074#if CONFIG_IS_ENABLED(CLK)
75 struct clk clk;
76 int ret;
77
78 ret = clk_get_by_index(dev, 1, &clk);
79 if (ret)
80 return ret;
81
82 host->bus_hz = clk_get_rate(&clk);
Pavel Machek51d21132014-09-08 14:08:45 +020083
Marek Vasut26608602018-08-01 18:28:35 +020084 clk_free(&clk);
85#else
86 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
87 host->bus_hz = cm_get_mmc_controller_clk_hz();
88#endif
89 if (host->bus_hz == 0) {
Marek Vasutae66f3c2015-11-30 20:41:04 +010090 printf("DWMMC: MMC clock is zero!");
Marek Vasut17497232015-07-25 10:48:14 +020091 return -EINVAL;
Chin Liang Seecca9f452013-12-30 18:26:14 -060092 }
93
Marek Vasut26608602018-08-01 18:28:35 +020094 return 0;
95}
96
97static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
98{
99 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
100 struct dwmci_host *host = &priv->host;
101 int fifo_depth;
102
Simon Glassdd79d6e2017-01-17 16:52:55 -0700103 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100104 "fifo-depth", 0);
Marek Vasut17497232015-07-25 10:48:14 +0200105 if (fifo_depth < 0) {
Marek Vasutae66f3c2015-11-30 20:41:04 +0100106 printf("DWMMC: Can't get FIFO depth\n");
Marek Vasut17497232015-07-25 10:48:14 +0200107 return -EINVAL;
108 }
109
Marek Vasutae66f3c2015-11-30 20:41:04 +0100110 host->name = dev->name;
Simon Glassba1dea42017-05-17 17:18:05 -0600111 host->ioaddr = (void *)devfdt_get_addr(dev);
Simon Glassdd79d6e2017-01-17 16:52:55 -0700112 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100113 "bus-width", 4);
Chin Liang Seecca9f452013-12-30 18:26:14 -0600114 host->clksel = socfpga_dwmci_clksel;
Marek Vasutae66f3c2015-11-30 20:41:04 +0100115
116 /*
117 * TODO(sjg@chromium.org): Remove the need for this hack.
118 * We only have one dwmmc block on gen5 SoCFPGA.
119 */
120 host->dev_index = 0;
Chin Liang Seecca9f452013-12-30 18:26:14 -0600121 host->fifoth_val = MSIZE(0x2) |
Marek Vasut17497232015-07-25 10:48:14 +0200122 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
Simon Glassdd79d6e2017-01-17 16:52:55 -0700123 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100124 "drvsel", 3);
Simon Glassdd79d6e2017-01-17 16:52:55 -0700125 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100126 "smplsel", 0);
Chin Liang See48e7bf92015-11-26 09:43:43 +0800127 host->priv = priv;
Chin Liang Seecca9f452013-12-30 18:26:14 -0600128
Marek Vasutae66f3c2015-11-30 20:41:04 +0100129 return 0;
Chin Liang Seecca9f452013-12-30 18:26:14 -0600130}
131
Marek Vasutae66f3c2015-11-30 20:41:04 +0100132static int socfpga_dwmmc_probe(struct udevice *dev)
Marek Vasut17497232015-07-25 10:48:14 +0200133{
Simon Glassa3a43202016-07-05 17:10:16 -0600134#ifdef CONFIG_BLK
135 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
136#endif
Marek Vasutae66f3c2015-11-30 20:41:04 +0100137 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
138 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
139 struct dwmci_host *host = &priv->host;
Marek Vasut26608602018-08-01 18:28:35 +0200140 int ret;
141
142 ret = socfpga_dwmmc_get_clk_rate(dev);
143 if (ret)
144 return ret;
Simon Glassa3a43202016-07-05 17:10:16 -0600145
Ley Foon Tan5a694d02018-06-14 18:45:21 +0800146 socfpga_dwmci_reset(dev);
147
Simon Glassa3a43202016-07-05 17:10:16 -0600148#ifdef CONFIG_BLK
Jaehoon Chungbf819d02016-09-23 19:13:16 +0900149 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
Simon Glassa3a43202016-07-05 17:10:16 -0600150 host->mmc = &plat->mmc;
151#else
Marek Vasut17497232015-07-25 10:48:14 +0200152
Marek Vasutae66f3c2015-11-30 20:41:04 +0100153 ret = add_dwmci(host, host->bus_hz, 400000);
154 if (ret)
155 return ret;
Simon Glassa3a43202016-07-05 17:10:16 -0600156#endif
157 host->mmc->priv = &priv->host;
Marek Vasutae66f3c2015-11-30 20:41:04 +0100158 upriv->mmc = host->mmc;
Simon Glass77ca42b2016-05-01 13:52:34 -0600159 host->mmc->dev = dev;
Marek Vasutae66f3c2015-11-30 20:41:04 +0100160
Patrick Bruenn3eab2202018-03-06 09:07:23 +0100161 return dwmci_probe(dev);
Marek Vasut17497232015-07-25 10:48:14 +0200162}
163
Simon Glassa3a43202016-07-05 17:10:16 -0600164static int socfpga_dwmmc_bind(struct udevice *dev)
165{
166#ifdef CONFIG_BLK
167 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
168 int ret;
169
170 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
171 if (ret)
172 return ret;
173#endif
174
175 return 0;
176}
177
Marek Vasutae66f3c2015-11-30 20:41:04 +0100178static const struct udevice_id socfpga_dwmmc_ids[] = {
179 { .compatible = "altr,socfpga-dw-mshc" },
180 { }
181};
Marek Vasut17497232015-07-25 10:48:14 +0200182
Marek Vasutae66f3c2015-11-30 20:41:04 +0100183U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
184 .name = "socfpga_dwmmc",
185 .id = UCLASS_MMC,
186 .of_match = socfpga_dwmmc_ids,
187 .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
Sylvain Lesne7083f912016-10-24 18:24:37 +0200188 .ops = &dm_dwmci_ops,
Simon Glassa3a43202016-07-05 17:10:16 -0600189 .bind = socfpga_dwmmc_bind,
Marek Vasutae66f3c2015-11-30 20:41:04 +0100190 .probe = socfpga_dwmmc_probe,
191 .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
Sylvain Lesne7083f912016-10-24 18:24:37 +0200192 .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100193};