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git01.mediatek.com / filogic / uboot / 68ad5757c9febca801664f801e5208349fe00cd9 / . / arch / riscv / dts / microchip-mpfs-icicle-kit.dts
blob: 287ef3d23b7385e073cafbe95784206d39077411 [file] [log] [blame]
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2021 Microchip Technology Inc.
4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]6
7/dts-v1/;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]8
9#include "microchip-mpfs.dtsi"
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]10
11/* Clock frequency (in Hz) of the rtcclk */
12#define RTCCLK_FREQ 1000000
13
14/ {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]15 model = "Microchip PolarFire-SoC Icicle Kit";
16 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]17
18 aliases {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]19 serial1 = &uart1;
20 ethernet0 = &mac1;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]21 };
22
23 chosen {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]24 stdout-path = "serial1";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]25 };
26
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]27 cpus {
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]28 timebase-frequency = <RTCCLK_FREQ>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]29 };
30
31 reserved-memory {
32 ranges;
33 #size-cells = <2>;
34 #address-cells = <2>;
35
36 fabricbuf0: fabricbuf@0 {
37 compatible = "shared-dma-pool";
38 reg = <0x0 0xae000000 0x0 0x2000000>;
39 label = "fabricbuf0-ddr-c";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]40 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]41
42 fabricbuf1: fabricbuf@1 {
43 compatible = "shared-dma-pool";
44 reg = <0x0 0xc0000000 0x0 0x8000000>;
45 label = "fabricbuf1-ddr-nc";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]46 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]47
48 fabricbuf2: fabricbuf@2 {
49 compatible = "shared-dma-pool";
50 reg = <0x0 0xd8000000 0x0 0x8000000>;
51 label = "fabricbuf2-ddr-nc-wcb";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]52 };
53 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]54
55 udmabuf0 {
56 compatible = "ikwzm,u-dma-buf";
57 device-name = "udmabuf-ddr-c0";
58 minor-number = <0>;
59 size = <0x0 0x2000000>;
60 memory-region = <&fabricbuf0>;
61 sync-mode = <3>;
62 };
63
64 udmabuf1 {
65 compatible = "ikwzm,u-dma-buf";
66 device-name = "udmabuf-ddr-nc0";
67 minor-number = <1>;
68 size = <0x0 0x8000000>;
69 memory-region = <&fabricbuf1>;
70 sync-mode = <3>;
71 };
72
73 udmabuf2 {
74 compatible = "ikwzm,u-dma-buf";
75 device-name = "udmabuf-ddr-nc-wcb0";
76 minor-number = <2>;
77 size = <0x0 0x8000000>;
78 memory-region = <&fabricbuf2>;
79 sync-mode = <3>;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]80 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]81
82 ddrc_cache_lo: memory@80000000 {
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]83 device_type = "memory";
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]84 reg = <0x0 0x80000000 0x0 0x2e000000>;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]85 clocks = <&clkcfg CLK_DDRC>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]86 status = "okay";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]87 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]88
89 ddrc_cache_hi: memory@1000000000 {
90 device_type = "memory";
91 reg = <0x10 0x0 0x0 0x40000000>;
92 clocks = <&clkcfg CLK_DDRC>;
93 status = "okay";
94 };
95};
96
97&uart1 {
98 status = "okay";
99};
100
101&mmc {
102 status = "okay";
103
104 bus-width = <4>;
105 disable-wp;
106 cap-mmc-highspeed;
107 cap-sd-highspeed;
108 card-detect-delay = <200>;
109 mmc-ddr-1_8v;
110 mmc-hs200-1_8v;
111 sd-uhs-sdr12;
112 sd-uhs-sdr25;
113 sd-uhs-sdr50;
114 sd-uhs-sdr104;
115};
116
117&i2c1 {
118 status = "okay";
119 clock-frequency = <100000>;
120
121 pac193x: pac193x@10 {
122 compatible = "microchip,pac1934";
123 reg = <0x10>;
124 samp-rate = <64>;
125 status = "okay";
126 ch1: channel0 {
127 uohms-shunt-res = <10000>;
128 rail-name = "VDDREG";
129 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]130 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]131 ch2: channel1 {
132 uohms-shunt-res = <10000>;
133 rail-name = "VDDA25";
134 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]135 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]136 ch3: channel2 {
137 uohms-shunt-res = <10000>;
138 rail-name = "VDD25";
139 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]140 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]141 ch4: channel3 {
142 uohms-shunt-res = <10000>;
143 rail-name = "VDDA_REG";
144 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]145 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]146 };
147};
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]148
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]149&mac1 {
150 status = "okay";
151 phy-mode = "sgmii";
152 phy-handle = <&phy1>;
153 phy1: ethernet-phy@9 {
154 reg = <9>;
155 ti,fifo-depth = <0x1>;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]156 };
157};