blob: 8beda9cb55720e95fff39450a2d17567090c3dec [file] [log] [blame]
Masahiro Yamada31adfc22016-01-19 13:55:28 +09001/*
2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <dm/device.h>
10
11DECLARE_GLOBAL_DATA_PTR;
12
13struct clk_fixed_rate {
14 unsigned long fixed_rate;
15};
16
17#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
18
19static ulong clk_fixed_rate_get_rate(struct udevice *dev)
20{
21 return to_clk_fixed_rate(dev)->fixed_rate;
22}
23
24static ulong clk_fixed_rate_get_periph_rate(struct udevice *dev, int periph)
25{
26 return clk_fixed_rate_get_rate(dev);
27}
28
29const struct clk_ops clk_fixed_rate_ops = {
30 .get_rate = clk_fixed_rate_get_rate,
31 .get_periph_rate = clk_fixed_rate_get_periph_rate,
32};
33
34static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
35{
36 to_clk_fixed_rate(dev)->fixed_rate =
37 fdtdec_get_int(gd->fdt_blob, dev->of_offset,
38 "clock-frequency", 0);
39
40 return 0;
41}
42
43static const struct udevice_id clk_fixed_rate_match[] = {
44 {
45 .compatible = "fixed-clock",
46 },
47 { /* sentinel */ }
48};
49
50U_BOOT_DRIVER(clk_fixed_rate) = {
51 .name = "fixed_rate_clock",
52 .id = UCLASS_CLK,
53 .of_match = clk_fixed_rate_match,
54 .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
55 .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
56 .ops = &clk_fixed_rate_ops,
57};