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git01.mediatek.com / filogic / uboot / 6894ea744d401b6d5b8cc68ebbe01edd0d309bbd / . / arch / arm / cpu / arm1176 / tnetv107x / mux.c
blob: 310d84dfb43e5512f1e85af910c2dd31d05d863f [file] [log] [blame]
Cyril Chemparathy692a7af2010-06-07 14:13:32 -0400[diff] [blame]1/*
2 * TNETV107X: Pinmux configuration
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Cyril Chemparathy692a7af2010-06-07 14:13:32 -0400[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/mux.h>
11
12#define MUX_MODE_1 0x00
13#define MUX_MODE_2 0x04
14#define MUX_MODE_3 0x0c
15#define MUX_MODE_4 0x1c
16
17#define MUX_DEBUG 0
18
19static const struct pin_config pin_table[] = {
20 /* reg shift mode */
21 TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
22 TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
23 TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
24 TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
25 TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
26 TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
27 TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
28 TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
29 TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
30 TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
31 TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
32 TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
33 TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
34 TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
35 TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
36 TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
37 TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
38 TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
39 TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
40 TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
41 TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
42 TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
43 TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
44 TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
45 TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
46 TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
47 TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
48 TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
49 TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
50 TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
51 TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
52 TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
53 TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
54 TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
55 TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
56 TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
57 TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
58 TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
59 TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
60 TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
61 TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
62 TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
63 TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
64 TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
65 TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
66 TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
67 TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
68 TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
69 TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
70 TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
71 TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
72 TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
73 TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
74 TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
75 TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
76 TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
77 TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
78 TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
79 TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
80 TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
81 TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
82 TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
83 TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
84 TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
85 TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
86 TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
87 TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
88 TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
89 TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
90 TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
91 TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
92 TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
93 TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
94 TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
95 TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
96 TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
97 TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
98 TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
99 TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
100 TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
101 TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
102 TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
103 TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
104 TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
105 TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
106 TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
107 TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
108 TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
109 TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
110 TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
111 TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
112 TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
113 TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
114 TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
115 TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
116 TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
117 TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
118 TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
119 TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
120 TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
121 TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
122 TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
123 TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
124 TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
125 TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
126 TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
127 TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
128 TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
129 TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
130 TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
131 TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
132 TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
133 TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
134 TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
135 TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
136 TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
137 TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
138 TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
139 TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
140 TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
141 TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
142 TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
143 TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
144 TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
145 TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
146 TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
147 TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
148 TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
149 TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
150 TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
151 TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
152 TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
153 TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
154 TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
155 TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
156 TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
157 TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
158 TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
159 TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
160 TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
161 TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
162 TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
163 TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
164 TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
165 TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
166 TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
167 TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
168 TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
169 TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
170 TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
171 TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
172 TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
173 TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
174 TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
175 TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
176 TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
177 TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
178 TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
179 TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
180 TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
181 TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
182 TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
183 TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
184 TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
185 TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
186 TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
187 TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
188 TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
189 TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
190 TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
191 TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
192 TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
193 TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
194 TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
195 TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
196 TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
197 TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
198 TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
199 TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
200 TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
201 TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
202 TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
203 TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
204 TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
205 TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
206 TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
207 TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
208 TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
209 TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
210 TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
211 TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
212 TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
213 TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
214 TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
215 TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
216 TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
217 TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
218 TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
219 TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
220 TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
221 TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
222 TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
223 TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
224 TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
225 TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
226 TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
227 TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
228 TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
229 TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
230 TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
231 TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
232 TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
233 TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
234 TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
235 TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
236 TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
237 TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
238 TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
239 TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
240 TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
241 TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
242 TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
243 TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
244 TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
245 TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
246 TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
247 TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
248 TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
249 TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
250 TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
251 TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
252 TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
253 TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
254 TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
255 TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
256 TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
257 TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
258 TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
259 TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
260 TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
261 TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
262 TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
263 TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
264 TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
265 TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
266 TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
267 TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
268 TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
269 TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
270 TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
271 TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
272 TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
273 TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
274 TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
275 TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
276 TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
277 TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
278 TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
279 TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
280 TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
281 TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
282 TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
283 TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
284 TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
285 TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
286 TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
287};
288
289const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
290
291int mux_select_pin(short index)
292{
293 const struct pin_config *cfg;
294 unsigned long mask, mode, reg;
295
296 if (index >= pin_table_size)
297 return 0;
298
299 cfg = &pin_table[index];
300
301 mask = 0x1f << cfg->mask_offset;
302 mode = cfg->mode << cfg->mask_offset;
303
304 reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
305 reg = (reg & ~mask) | mode;
306 __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
307
308 return 1;
309}
310
311int mux_select_pins(const short *pins)
312{
313 int i, ret = 1;
314
315 for (i = 0; pins[i] >= 0; i++)
316 ret &= mux_select_pin(pins[i]);
317
318 return ret;
319}