wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * CPU specific code for the MPC8260 |
| 26 | * |
| 27 | * written or collected and sometimes rewritten by |
| 28 | * Magnus Damm <damm@bitsmart.com> |
| 29 | * |
| 30 | * minor modifications by |
| 31 | * Wolfgang Denk <wd@denx.de> |
| 32 | * |
| 33 | * modified for 8260 by |
| 34 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> |
| 35 | * |
| 36 | * added 8260 masks by |
| 37 | * Marius Groeger <mag@sysgo.de> |
| 38 | */ |
| 39 | |
| 40 | #include <common.h> |
| 41 | #include <watchdog.h> |
| 42 | #include <command.h> |
| 43 | #include <mpc8260.h> |
| 44 | #include <asm/processor.h> |
| 45 | #include <asm/cpm_8260.h> |
| 46 | |
| 47 | int checkcpu (void) |
| 48 | { |
| 49 | DECLARE_GLOBAL_DATA_PTR; |
| 50 | |
| 51 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 52 | ulong clock = gd->cpu_clk; |
| 53 | uint pvr = get_pvr (); |
| 54 | uint immr, rev, m, k; |
| 55 | char buf[32]; |
| 56 | |
| 57 | puts ("CPU: "); |
| 58 | |
| 59 | if (((pvr >> 16) & 0xff) != 0x81) |
| 60 | return -1; /* whoops! not an MPC8260 */ |
| 61 | rev = pvr & 0xff; |
| 62 | |
| 63 | immr = immap->im_memctl.memc_immr; |
| 64 | if ((immr & IMMR_ISB_MSK) != CFG_IMMR) |
| 65 | return -1; /* whoops! someone moved the IMMR */ |
| 66 | |
| 67 | printf ("MPC8260 (Rev %02x, Mask ", rev); |
| 68 | |
| 69 | /* |
| 70 | * the bottom 16 bits of the immr are the Part Number and Mask Number |
| 71 | * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the |
| 72 | * RISC Microcode Revision Number (13-10). |
| 73 | * For the 8260, Motorola doesn't include the Microcode Revision |
| 74 | * in the mask. |
| 75 | */ |
| 76 | m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK); |
| 77 | k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]); |
| 78 | |
| 79 | switch (m) { |
| 80 | case 0x0000: |
| 81 | printf ("0.2 2J24M"); |
| 82 | break; |
| 83 | case 0x0010: |
| 84 | printf ("A.0 K22A"); |
| 85 | break; |
| 86 | case 0x0011: |
| 87 | printf ("A.1 1K22A-XC"); |
| 88 | break; |
| 89 | case 0x0001: |
| 90 | printf ("B.1 1K23A"); |
| 91 | break; |
| 92 | case 0x0021: |
| 93 | printf ("B.2 2K23A-XC"); |
| 94 | break; |
| 95 | case 0x0023: |
| 96 | printf ("B.3 3K23A"); |
| 97 | break; |
| 98 | case 0x0024: |
| 99 | printf ("C.2 6K23A"); |
| 100 | break; |
| 101 | case 0x0060: |
| 102 | printf ("A.0(A) 2K25A"); |
| 103 | break; |
| 104 | default: |
| 105 | printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); |
| 106 | break; |
| 107 | } |
| 108 | |
| 109 | printf (") at %s MHz\n", strmhz (buf, clock)); |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | /* ------------------------------------------------------------------------- */ |
| 115 | /* configures a UPM by writing into the UPM RAM array */ |
| 116 | /* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */ |
| 117 | /* NOTE: the physical address chosen must not overlap into any other area */ |
| 118 | /* mapped by the memory controller because bank 11 has the lowest priority */ |
| 119 | |
| 120 | void upmconfig (uint upm, uint * table, uint size) |
| 121 | { |
| 122 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 123 | volatile memctl8260_t *memctl = &immap->im_memctl; |
| 124 | volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */ |
| 125 | uint i; |
| 126 | |
| 127 | /* first set up bank 11 to reference the correct UPM at a dummy address */ |
| 128 | |
| 129 | memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */ |
| 130 | |
| 131 | switch (upm) { |
| 132 | |
| 133 | case UPMA: |
| 134 | memctl->memc_br11 = |
| 135 | ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA | |
| 136 | BRx_V; |
| 137 | memctl->memc_mamr = MxMR_OP_WARR; |
| 138 | break; |
| 139 | |
| 140 | case UPMB: |
| 141 | memctl->memc_br11 = |
| 142 | ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB | |
| 143 | BRx_V; |
| 144 | memctl->memc_mbmr = MxMR_OP_WARR; |
| 145 | break; |
| 146 | |
| 147 | case UPMC: |
| 148 | memctl->memc_br11 = |
| 149 | ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC | |
| 150 | BRx_V; |
| 151 | memctl->memc_mcmr = MxMR_OP_WARR; |
| 152 | break; |
| 153 | |
| 154 | default: |
| 155 | panic ("upmconfig passed invalid UPM number (%u)\n", upm); |
| 156 | break; |
| 157 | |
| 158 | } |
| 159 | |
| 160 | /* |
| 161 | * at this point, the dummy address is set up to access the selected UPM, |
| 162 | * the MAD pointer is zero, and the MxMR OP is set for writing to RAM |
| 163 | * |
| 164 | * now we simply load the mdr with each word and poke the dummy address. |
| 165 | * the MAD is incremented on each access. |
| 166 | */ |
| 167 | |
| 168 | for (i = 0; i < size; i++) { |
| 169 | memctl->memc_mdr = table[i]; |
| 170 | *dummy = 0; |
| 171 | } |
| 172 | |
| 173 | /* now kill bank 11 */ |
| 174 | memctl->memc_br11 = 0; |
| 175 | } |
| 176 | |
| 177 | /* ------------------------------------------------------------------------- */ |
| 178 | |
| 179 | int |
| 180 | do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) |
| 181 | { |
| 182 | ulong msr, addr; |
| 183 | |
| 184 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 185 | |
| 186 | immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */ |
| 187 | |
| 188 | /* Interrupts and MMU off */ |
| 189 | __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); |
| 190 | |
| 191 | msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); |
| 192 | __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); |
| 193 | |
| 194 | /* |
| 195 | * Trying to execute the next instruction at a non-existing address |
| 196 | * should cause a machine check, resulting in reset |
| 197 | */ |
| 198 | #ifdef CFG_RESET_ADDRESS |
| 199 | addr = CFG_RESET_ADDRESS; |
| 200 | #else |
| 201 | /* |
| 202 | * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE |
| 203 | * - sizeof (ulong) is usually a valid address. Better pick an address |
| 204 | * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. |
| 205 | */ |
| 206 | addr = CFG_MONITOR_BASE - sizeof (ulong); |
| 207 | #endif |
| 208 | ((void (*)(void)) addr) (); |
| 209 | return 1; |
| 210 | |
| 211 | } |
| 212 | |
| 213 | /* ------------------------------------------------------------------------- */ |
| 214 | |
| 215 | /* |
| 216 | * Get timebase clock frequency (like cpu_clk in Hz) |
| 217 | * |
| 218 | */ |
| 219 | unsigned long get_tbclk (void) |
| 220 | { |
| 221 | DECLARE_GLOBAL_DATA_PTR; |
| 222 | |
| 223 | ulong tbclk; |
| 224 | |
| 225 | tbclk = (gd->bus_clk + 3L) / 4L; |
| 226 | |
| 227 | return (tbclk); |
| 228 | } |
| 229 | |
| 230 | /* ------------------------------------------------------------------------- */ |
| 231 | |
| 232 | #if defined(CONFIG_WATCHDOG) |
| 233 | void watchdog_reset (void) |
| 234 | { |
| 235 | int re_enable = disable_interrupts (); |
| 236 | |
| 237 | reset_8260_watchdog ((immap_t *) CFG_IMMR); |
| 238 | if (re_enable) |
| 239 | enable_interrupts (); |
| 240 | } |
| 241 | #endif /* CONFIG_WATCHDOG */ |
| 242 | |
| 243 | /* ------------------------------------------------------------------------- */ |