| wdenk | c00b5f8 | 2002-11-03 11:12:02 +0000 | [diff] [blame] | 1 | /*----------------------------------------------------------------------------+ |
| 2 | | |
| 3 | | This source code has been made available to you by IBM on an AS-IS |
| 4 | | basis. Anyone receiving this source is licensed under IBM |
| 5 | | copyrights to use it in any way he or she deems fit, including |
| 6 | | copying it, modifying it, compiling it, and redistributing it either |
| 7 | | with or without modifications. No license under IBM patents or |
| 8 | | patent applications is to be implied by the copyright license. |
| 9 | | |
| 10 | | Any user of this software should understand that IBM cannot provide |
| 11 | | technical support for this software and will not be responsible for |
| 12 | | any consequences resulting from the use of this software. |
| 13 | | |
| 14 | | Any person who transfers this source code or any derivative work |
| 15 | | must include the IBM copyright notice, this paragraph, and the |
| 16 | | preceding two paragraphs in the transferred software. |
| 17 | | |
| 18 | | COPYRIGHT I B M CORPORATION 1999 |
| 19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
| 20 | +----------------------------------------------------------------------------*/ |
| 21 | |
| 22 | #ifndef __PPC440_H__ |
| 23 | #define __PPC440_H__ |
| 24 | |
| 25 | /*--------------------------------------------------------------------- */ |
| 26 | /* Special Purpose Registers */ |
| 27 | /*--------------------------------------------------------------------- */ |
| 28 | #define dec 0x016 /* decrementer */ |
| 29 | #define srr0 0x01a /* save/restore register 0 */ |
| 30 | #define srr1 0x01b /* save/restore register 1 */ |
| 31 | #define pid 0x030 /* process id */ |
| 32 | #define decar 0x036 /* decrementer auto-reload */ |
| 33 | #define csrr0 0x03a /* critical save/restore register 0 */ |
| 34 | #define csrr1 0x03b /* critical save/restore register 1 */ |
| 35 | #define dear 0x03d /* data exception address register */ |
| 36 | #define esr 0x03e /* exception syndrome register */ |
| 37 | #define ivpr 0x03f /* interrupt prefix register */ |
| 38 | #define usprg0 0x100 /* user special purpose register general 0 */ |
| 39 | #define usprg1 0x110 /* user special purpose register general 1 */ |
| 40 | #define sprg1 0x111 /* special purpose register general 1 */ |
| 41 | #define sprg2 0x112 /* special purpose register general 2 */ |
| 42 | #define sprg3 0x113 /* special purpose register general 3 */ |
| 43 | #define sprg4 0x114 /* special purpose register general 4 */ |
| 44 | #define sprg5 0x115 /* special purpose register general 5 */ |
| 45 | #define sprg6 0x116 /* special purpose register general 6 */ |
| 46 | #define sprg7 0x117 /* special purpose register general 7 */ |
| 47 | #define tbl 0x11c /* time base lower (supervisor)*/ |
| 48 | #define tbu 0x11d /* time base upper (supervisor)*/ |
| 49 | #define pir 0x11e /* processor id register */ |
| 50 | /*#define pvr 0x11f processor version register */ |
| 51 | #define dbsr 0x130 /* debug status register */ |
| 52 | #define dbcr0 0x134 /* debug control register 0 */ |
| 53 | #define dbcr1 0x135 /* debug control register 1 */ |
| 54 | #define dbcr2 0x136 /* debug control register 2 */ |
| 55 | #define iac1 0x138 /* instruction address compare 1 */ |
| 56 | #define iac2 0x139 /* instruction address compare 2 */ |
| 57 | #define iac3 0x13a /* instruction address compare 3 */ |
| 58 | #define iac4 0x13b /* instruction address compare 4 */ |
| 59 | #define dac1 0x13c /* data address compare 1 */ |
| 60 | #define dac2 0x13d /* data address compare 2 */ |
| 61 | #define dvc1 0x13e /* data value compare 1 */ |
| 62 | #define dvc2 0x13f /* data value compare 2 */ |
| 63 | #define tsr 0x150 /* timer status register */ |
| 64 | #define tcr 0x154 /* timer control register */ |
| 65 | #define ivor0 0x190 /* interrupt vector offset register 0 */ |
| 66 | #define ivor1 0x191 /* interrupt vector offset register 1 */ |
| 67 | #define ivor2 0x192 /* interrupt vector offset register 2 */ |
| 68 | #define ivor3 0x193 /* interrupt vector offset register 3 */ |
| 69 | #define ivor4 0x194 /* interrupt vector offset register 4 */ |
| 70 | #define ivor5 0x195 /* interrupt vector offset register 5 */ |
| 71 | #define ivor6 0x196 /* interrupt vector offset register 6 */ |
| 72 | #define ivor7 0x197 /* interrupt vector offset register 7 */ |
| 73 | #define ivor8 0x198 /* interrupt vector offset register 8 */ |
| 74 | #define ivor9 0x199 /* interrupt vector offset register 9 */ |
| 75 | #define ivor10 0x19a /* interrupt vector offset register 10 */ |
| 76 | #define ivor11 0x19b /* interrupt vector offset register 11 */ |
| 77 | #define ivor12 0x19c /* interrupt vector offset register 12 */ |
| 78 | #define ivor13 0x19d /* interrupt vector offset register 13 */ |
| 79 | #define ivor14 0x19e /* interrupt vector offset register 14 */ |
| 80 | #define ivor15 0x19f /* interrupt vector offset register 15 */ |
| 81 | #define inv0 0x370 /* instruction cache normal victim 0 */ |
| 82 | #define inv1 0x371 /* instruction cache normal victim 1 */ |
| 83 | #define inv2 0x372 /* instruction cache normal victim 2 */ |
| 84 | #define inv3 0x373 /* instruction cache normal victim 3 */ |
| 85 | #define itv0 0x374 /* instruction cache transient victim 0 */ |
| 86 | #define itv1 0x375 /* instruction cache transient victim 1 */ |
| 87 | #define itv2 0x376 /* instruction cache transient victim 2 */ |
| 88 | #define itv3 0x377 /* instruction cache transient victim 3 */ |
| 89 | #define dnv0 0x390 /* data cache normal victim 0 */ |
| 90 | #define dnv1 0x391 /* data cache normal victim 1 */ |
| 91 | #define dnv2 0x392 /* data cache normal victim 2 */ |
| 92 | #define dnv3 0x393 /* data cache normal victim 3 */ |
| 93 | #define dtv0 0x394 /* data cache transient victim 0 */ |
| 94 | #define dtv1 0x395 /* data cache transient victim 1 */ |
| 95 | #define dtv2 0x396 /* data cache transient victim 2 */ |
| 96 | #define dtv3 0x397 /* data cache transient victim 3 */ |
| 97 | #define dvlim 0x398 /* data cache victim limit */ |
| 98 | #define ivlim 0x399 /* instruction cache victim limit */ |
| 99 | #define rstcfg 0x39b /* reset configuration */ |
| 100 | #define dcdbtrl 0x39c /* data cache debug tag register low */ |
| 101 | #define dcdbtrh 0x39d /* data cache debug tag register high */ |
| 102 | #define icdbtrl 0x39e /* instruction cache debug tag register low */ |
| 103 | #define icdbtrh 0x39f /* instruction cache debug tag register high */ |
| 104 | #define mmucr 0x3b2 /* mmu control register */ |
| 105 | #define ccr0 0x3b3 /* core configuration register 0 */ |
| 106 | #define icdbdr 0x3d3 /* instruction cache debug data register */ |
| 107 | #define dbdr 0x3f3 /* debug data register */ |
| 108 | |
| 109 | /****************************************************************************** |
| 110 | * DCRs & Related |
| 111 | ******************************************************************************/ |
| 112 | |
| 113 | /*----------------------------------------------------------------------------- |
| 114 | | SDRAM Controller |
| 115 | +----------------------------------------------------------------------------*/ |
| 116 | #define SDRAM_DCR_BASE 0x10 |
| 117 | #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ |
| 118 | #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ |
| 119 | |
| 120 | /* values for memcfga register - indirect addressing of these regs */ |
| 121 | #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ |
| 122 | #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ |
| 123 | #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ |
| 124 | #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ |
| 125 | #define mem_bear 0x0010 /* bus error address reg */ |
| 126 | #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ |
| 127 | #define mem_mirq_set 0x0012 /* bus master interrupt (set) */ |
| 128 | #define mem_slio 0x0018 /* ddr sdram slave interface options */ |
| 129 | #define mem_cfg0 0x0020 /* ddr sdram options 0 */ |
| 130 | #define mem_cfg1 0x0021 /* ddr sdram options 1 */ |
| 131 | #define mem_devopt 0x0022 /* ddr sdram device options */ |
| 132 | #define mem_mcsts 0x0024 /* memory controller status */ |
| 133 | #define mem_rtr 0x0030 /* refresh timer register */ |
| 134 | #define mem_pmit 0x0034 /* power management idle timer */ |
| 135 | #define mem_uabba 0x0038 /* plb UABus base address */ |
| 136 | #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ |
| 137 | #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ |
| 138 | #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ |
| 139 | #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ |
| 140 | #define mem_tr0 0x0080 /* sdram timing register 0 */ |
| 141 | #define mem_tr1 0x0081 /* sdram timing register 1 */ |
| 142 | #define mem_clktr 0x0082 /* ddr clock timing register */ |
| 143 | #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ |
| 144 | #define mem_dlycal 0x0084 /* delay line calibration register */ |
| 145 | #define mem_eccesr 0x0098 /* ECC error status */ |
| 146 | |
| 147 | /*----------------------------------------------------------------------------- |
| 148 | | Extrnal Bus Controller |
| 149 | +----------------------------------------------------------------------------*/ |
| 150 | #define EBC_DCR_BASE 0x12 |
| 151 | #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ |
| 152 | #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ |
| 153 | /* values for ebccfga register - indirect addressing of these regs */ |
| 154 | #define pb0cr 0x00 /* periph bank 0 config reg */ |
| 155 | #define pb1cr 0x01 /* periph bank 1 config reg */ |
| 156 | #define pb2cr 0x02 /* periph bank 2 config reg */ |
| 157 | #define pb3cr 0x03 /* periph bank 3 config reg */ |
| 158 | #define pb4cr 0x04 /* periph bank 4 config reg */ |
| 159 | #define pb5cr 0x05 /* periph bank 5 config reg */ |
| 160 | #define pb6cr 0x06 /* periph bank 6 config reg */ |
| 161 | #define pb7cr 0x07 /* periph bank 7 config reg */ |
| 162 | #define pb0ap 0x10 /* periph bank 0 access parameters */ |
| 163 | #define pb1ap 0x11 /* periph bank 1 access parameters */ |
| 164 | #define pb2ap 0x12 /* periph bank 2 access parameters */ |
| 165 | #define pb3ap 0x13 /* periph bank 3 access parameters */ |
| 166 | #define pb4ap 0x14 /* periph bank 4 access parameters */ |
| 167 | #define pb5ap 0x15 /* periph bank 5 access parameters */ |
| 168 | #define pb6ap 0x16 /* periph bank 6 access parameters */ |
| 169 | #define pb7ap 0x17 /* periph bank 7 access parameters */ |
| 170 | #define pbear 0x20 /* periph bus error addr reg */ |
| 171 | #define pbesr 0x21 /* periph bus error status reg */ |
| 172 | #define xbcfg 0x23 /* external bus configuration reg */ |
| 173 | #define xbcid 0x23 /* external bus core id reg */ |
| 174 | |
| 175 | /*----------------------------------------------------------------------------- |
| 176 | | Internal SRAM |
| 177 | +----------------------------------------------------------------------------*/ |
| 178 | #define ISRAM0_DCR_BASE 0x020 |
| 179 | #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ |
| 180 | #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ |
| 181 | #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ |
| 182 | #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ |
| 183 | #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ |
| 184 | #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ |
| 185 | #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ |
| 186 | #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ |
| 187 | #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ |
| 188 | #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ |
| 189 | #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ |
| 190 | |
| 191 | /*----------------------------------------------------------------------------- |
| 192 | | On-Chip Buses |
| 193 | +----------------------------------------------------------------------------*/ |
| 194 | /* TODO: as needed */ |
| 195 | |
| 196 | /*----------------------------------------------------------------------------- |
| 197 | | Clocking, Power Management and Chip Control |
| 198 | +----------------------------------------------------------------------------*/ |
| 199 | #define CNTRL_DCR_BASE 0x0b0 |
| 200 | |
| 201 | #define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */ |
| 202 | #define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */ |
| 203 | #define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */ |
| 204 | |
| 205 | #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ |
| 206 | #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ |
| 207 | #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ |
| 208 | #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ |
| 209 | |
| 210 | #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ |
| 211 | #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ |
| 212 | #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ |
| 213 | #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ |
| 214 | |
| 215 | #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ |
| 216 | #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ |
| 217 | |
| 218 | /*----------------------------------------------------------------------------- |
| 219 | | Universal interrupt controller |
| 220 | +----------------------------------------------------------------------------*/ |
| 221 | #define UIC0_DCR_BASE 0xc0 |
| 222 | #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ |
| 223 | #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ |
| 224 | #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ |
| 225 | #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ |
| 226 | #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ |
| 227 | #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ |
| 228 | #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ |
| 229 | #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ |
| 230 | |
| 231 | #define UIC1_DCR_BASE 0xd0 |
| 232 | #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ |
| 233 | #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ |
| 234 | #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ |
| 235 | #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ |
| 236 | #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ |
| 237 | #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ |
| 238 | #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ |
| 239 | #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ |
| 240 | |
| 241 | /* The following is for compatibility with 405 code */ |
| 242 | #define uicsr uic0sr |
| 243 | #define uicer uic0er |
| 244 | #define uiccr uic0cr |
| 245 | #define uicpr uic0pr |
| 246 | #define uictr uic0tr |
| 247 | #define uicmsr uic0msr |
| 248 | #define uicvr uic0vr |
| 249 | #define uicvcr uic0vcr |
| 250 | |
| 251 | /*----------------------------------------------------------------------------- |
| 252 | | DMA |
| 253 | +----------------------------------------------------------------------------*/ |
| 254 | #define DMA_DCR_BASE 0x100 |
| 255 | #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ |
| 256 | #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ |
| 257 | #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ |
| 258 | #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ |
| 259 | #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ |
| 260 | #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ |
| 261 | #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ |
| 262 | #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ |
| 263 | #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ |
| 264 | #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ |
| 265 | #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ |
| 266 | #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ |
| 267 | #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ |
| 268 | #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ |
| 269 | #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ |
| 270 | #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ |
| 271 | #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ |
| 272 | #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ |
| 273 | #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ |
| 274 | #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ |
| 275 | #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ |
| 276 | #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ |
| 277 | #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ |
| 278 | #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ |
| 279 | #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ |
| 280 | #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ |
| 281 | #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ |
| 282 | #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ |
| 283 | #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ |
| 284 | #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ |
| 285 | #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ |
| 286 | #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ |
| 287 | #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ |
| 288 | #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ |
| 289 | #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ |
| 290 | #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ |
| 291 | |
| 292 | /*----------------------------------------------------------------------------- |
| 293 | | Memory Access Layer |
| 294 | +----------------------------------------------------------------------------*/ |
| 295 | #define MAL_DCR_BASE 0x180 |
| 296 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ |
| 297 | #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ |
| 298 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ |
| 299 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ |
| 300 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ |
| 301 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ |
| 302 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ |
| 303 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ |
| 304 | #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ |
| 305 | #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ |
| 306 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ |
| 307 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ |
| 308 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ |
| 309 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ |
| 310 | #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ |
| 311 | #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ |
| 312 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ |
| 313 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ |
| 314 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ |
| 315 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ |
| 316 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ |
| 317 | |
| 318 | /*---------------------------------------------------------------------------+ |
| 319 | | Universal interrupt controller 0 interrupts (UIC0) |
| 320 | +---------------------------------------------------------------------------*/ |
| 321 | #define UIC_U0 0x80000000 /* UART 0 */ |
| 322 | #define UIC_U1 0x40000000 /* UART 1 */ |
| 323 | #define UIC_IIC0 0x20000000 /* IIC */ |
| 324 | #define UIC_IIC1 0x10000000 /* IIC */ |
| 325 | #define UIC_PIM 0x08000000 /* PCI inbound message */ |
| 326 | #define UIC_PCRW 0x04000000 /* PCI command register write */ |
| 327 | #define UIC_PPM 0x02000000 /* PCI power management */ |
| 328 | #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ |
| 329 | #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ |
| 330 | #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ |
| 331 | #define UIC_MTE 0x00200000 /* MAL TXEOB */ |
| 332 | #define UIC_MRE 0x00100000 /* MAL RXEOB */ |
| 333 | #define UIC_D0 0x00080000 /* DMA channel 0 */ |
| 334 | #define UIC_D1 0x00040000 /* DMA channel 1 */ |
| 335 | #define UIC_D2 0x00020000 /* DMA channel 2 */ |
| 336 | #define UIC_D3 0x00010000 /* DMA channel 3 */ |
| 337 | #define UIC_RSVD0 0x00008000 /* Reserved */ |
| 338 | #define UIC_RSVD1 0x00004000 /* Reserved */ |
| 339 | #define UIC_CT0 0x00002000 /* GPT compare timer 0 */ |
| 340 | #define UIC_CT1 0x00001000 /* GPT compare timer 1 */ |
| 341 | #define UIC_CT2 0x00000800 /* GPT compare timer 2 */ |
| 342 | #define UIC_CT3 0x00000400 /* GPT compare timer 3 */ |
| 343 | #define UIC_CT4 0x00000200 /* GPT compare timer 4 */ |
| 344 | #define UIC_EIR0 0x00000100 /* External interrupt 0 */ |
| 345 | #define UIC_EIR1 0x00000080 /* External interrupt 1 */ |
| 346 | #define UIC_EIR2 0x00000040 /* External interrupt 2 */ |
| 347 | #define UIC_EIR3 0x00000020 /* External interrupt 3 */ |
| 348 | #define UIC_EIR4 0x00000010 /* External interrupt 4 */ |
| 349 | #define UIC_EIR5 0x00000008 /* External interrupt 5 */ |
| 350 | #define UIC_EIR6 0x00000004 /* External interrupt 6 */ |
| 351 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ |
| 352 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ |
| 353 | |
| 354 | /* For compatibility with 405 code */ |
| 355 | #define UIC_MAL_TXEOB UIC_MTE |
| 356 | #define UIC_MAL_RXEOB UIC_MRE |
| 357 | |
| 358 | /*---------------------------------------------------------------------------+ |
| 359 | | Universal interrupt controller 1 interrupts (UIC1) |
| 360 | +---------------------------------------------------------------------------*/ |
| 361 | #define UIC_MS 0x80000000 /* MAL SERR */ |
| 362 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ |
| 363 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ |
| 364 | #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ |
| 365 | #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ |
| 366 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ |
| 367 | #define UIC_EBMI 0x02000000 /* EBMI interrupt status */ |
| 368 | #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ |
| 369 | #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ |
| 370 | #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ |
| 371 | #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ |
| 372 | #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ |
| 373 | #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ |
| 374 | #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ |
| 375 | #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ |
| 376 | #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ |
| 377 | #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ |
| 378 | #define UIC_PPMI 0x00004000 /* PPM interrupt status */ |
| 379 | #define UIC_EIR7 0x00002000 /* External interrupt 7 */ |
| 380 | #define UIC_EIR8 0x00001000 /* External interrupt 8 */ |
| 381 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ |
| 382 | #define UIC_EIR10 0x00000400 /* External interrupt 10 */ |
| 383 | #define UIC_EIR11 0x00000200 /* External interrupt 11 */ |
| 384 | #define UIC_EIR12 0x00000100 /* External interrupt 12 */ |
| 385 | #define UIC_SRE 0x00000080 /* Serial ROM error */ |
| 386 | #define UIC_RSVD2 0x00000040 /* Reserved */ |
| 387 | #define UIC_RSVD3 0x00000020 /* Reserved */ |
| 388 | #define UIC_PAE 0x00000010 /* PCI asynchronous error */ |
| 389 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ |
| 390 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ |
| 391 | #define UIC_ETH1 0x00000002 /* Ethernet 1 */ |
| 392 | #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ |
| 393 | |
| 394 | /* For compatibility with 405 code */ |
| 395 | #define UIC_MAL_SERR UIC_MS |
| 396 | #define UIC_MAL_TXDE UIC_MTDE |
| 397 | #define UIC_MAL_RXDE UIC_MRDE |
| 398 | #define UIC_ENET UIC_ETH0 |
| 399 | |
| 400 | /*-----------------------------------------------------------------------------+ |
| 401 | | Clocking |
| 402 | +-----------------------------------------------------------------------------*/ |
| 403 | #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ |
| 404 | #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ |
| 405 | #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ |
| 406 | #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ |
| 407 | #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ |
| 408 | #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ |
| 409 | #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ |
| 410 | #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ |
| 411 | #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ |
| 412 | #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ |
| 413 | #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ |
| 414 | #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ |
| 415 | |
| 416 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ |
| 417 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ |
| 418 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ |
| 419 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ |
| 420 | |
| 421 | /*----------------------------------------------------------------------------- |
| 422 | | IIC Register Offsets |
| 423 | '----------------------------------------------------------------------------*/ |
| 424 | #define IICMDBUF 0x00 |
| 425 | #define IICSDBUF 0x02 |
| 426 | #define IICLMADR 0x04 |
| 427 | #define IICHMADR 0x05 |
| 428 | #define IICCNTL 0x06 |
| 429 | #define IICMDCNTL 0x07 |
| 430 | #define IICSTS 0x08 |
| 431 | #define IICEXTSTS 0x09 |
| 432 | #define IICLSADR 0x0A |
| 433 | #define IICHSADR 0x0B |
| 434 | #define IICCLKDIV 0x0C |
| 435 | #define IICINTRMSK 0x0D |
| 436 | #define IICXFRCNT 0x0E |
| 437 | #define IICXTCNTLSS 0x0F |
| 438 | #define IICDIRECTCNTL 0x10 |
| 439 | |
| 440 | /*----------------------------------------------------------------------------- |
| 441 | | UART Register Offsets |
| 442 | '----------------------------------------------------------------------------*/ |
| 443 | #define DATA_REG 0x00 |
| 444 | #define DL_LSB 0x00 |
| 445 | #define DL_MSB 0x01 |
| 446 | #define INT_ENABLE 0x01 |
| 447 | #define FIFO_CONTROL 0x02 |
| 448 | #define LINE_CONTROL 0x03 |
| 449 | #define MODEM_CONTROL 0x04 |
| 450 | #define LINE_STATUS 0x05 |
| 451 | #define MODEM_STATUS 0x06 |
| 452 | #define SCRATCH 0x07 |
| 453 | |
| 454 | /*----------------------------------------------------------------------------- |
| 455 | | PCI Internal Registers et. al. (accessed via plb) |
| 456 | +----------------------------------------------------------------------------*/ |
| 457 | #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) |
| 458 | #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004) |
| 459 | #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) |
| 460 | #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) |
| 461 | |
| 462 | #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) |
| 463 | #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) |
| 464 | #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) |
| 465 | #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS ) |
| 466 | #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID ) |
| 467 | #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE) |
| 468 | #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE ) |
| 469 | #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER ) |
| 470 | #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE ) |
| 471 | #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST ) |
| 472 | #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 ) |
| 473 | #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 ) |
| 474 | #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 ) |
| 475 | #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 ) |
| 476 | #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 ) |
| 477 | #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 ) |
| 478 | #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS ) |
| 479 | #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) |
| 480 | #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID ) |
| 481 | #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS ) |
| 482 | #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST ) |
| 483 | #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 ) |
| 484 | #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 ) |
| 485 | #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 ) |
| 486 | #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE ) |
| 487 | #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN ) |
| 488 | #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT ) |
| 489 | #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT ) |
| 490 | |
| 491 | #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040) |
| 492 | #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044) |
| 493 | |
| 494 | #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068) |
| 495 | #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c) |
| 496 | #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070) |
| 497 | #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074) |
| 498 | #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078) |
| 499 | #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c) |
| 500 | #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080) |
| 501 | #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084) |
| 502 | #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088) |
| 503 | #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c) |
| 504 | #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090) |
| 505 | |
| 506 | #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098) |
| 507 | #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c) |
| 508 | #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0) |
| 509 | #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4) |
| 510 | #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8) |
| 511 | #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac) |
| 512 | #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0) |
| 513 | #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4) |
| 514 | #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8) |
| 515 | |
| 516 | #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) |
| 517 | |
| 518 | /* |
| 519 | * Macros for accessing the indirect EBC registers |
| 520 | */ |
| 521 | #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) |
| 522 | #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) |
| 523 | |
| 524 | /* |
| 525 | * Macros for accessing the indirect SDRAM controller registers |
| 526 | */ |
| 527 | #define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) |
| 528 | #define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd) |
| 529 | |
| 530 | |
| 531 | #ifndef __ASSEMBLY__ |
| 532 | |
| 533 | typedef struct |
| 534 | { |
| 535 | unsigned long pllFwdDivA; |
| 536 | unsigned long pllFwdDivB; |
| 537 | unsigned long pllFbkDiv; |
| 538 | unsigned long pllOpbDiv; |
| 539 | unsigned long pllExtBusDiv; |
| 540 | unsigned long freqVCOMhz; /* in MHz */ |
| 541 | unsigned long freqProcessor; |
| 542 | unsigned long freqPLB; |
| 543 | unsigned long freqOPB; |
| 544 | unsigned long freqEPB; |
| 545 | } PPC440_SYS_INFO; |
| 546 | |
| 547 | #endif /* _ASMLANGUAGE */ |
| 548 | |
| 549 | #define RESET_VECTOR 0xfffffffc |
| 550 | #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache |
| 551 | line aligned data. */ |
| 552 | |
| 553 | #endif /* __PPC440_H__ */ |
| 554 | |