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git01.mediatek.com / filogic / uboot / 67f97d1bcafca0236eaf1c195e2bda9ae8d05fc5 / . / drivers / firmware / ti_sci_static_data.h
blob: 789f0c6b2d9038bf0504bbffc83cee1d99ad9c2e [file] [log] [blame]
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]1/* SPDX-License-Identifier: BSD-3-Clause */
2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]4 *
5 */
6
7#ifndef __TI_SCI_STATIC_DATA_H
8#define __TI_SCI_STATIC_DATA_H
9
10struct ti_sci_resource_static_data {
11 u32 dev_id;
12 u16 range_start;
13 u16 range_num;
14 u8 subtype;
15};
16
17#if IS_ENABLED(CONFIG_K3_DM_FW)
18
Vignesh Raghavendra818c9392022-06-15 19:33:05 +0530[diff] [blame]19#if IS_ENABLED(CONFIG_SOC_K3_J721E)
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]20static struct ti_sci_resource_static_data rm_static_data[] = {
21 /* Free rings */
22 {
23 .dev_id = 235,
24 .subtype = 1,
25 .range_start = 124,
26 .range_num = 32,
27 },
28 /* TX channels */
29 {
30 .dev_id = 236,
31 .subtype = 13,
32 .range_start = 6,
33 .range_num = 2,
34 },
35 /* RX channels */
36 {
37 .dev_id = 236,
38 .subtype = 10,
39 .range_start = 6,
40 .range_num = 2,
41 },
42 /* RX Free flows */
43 {
44 .dev_id = 236,
45 .subtype = 0,
46 .range_start = 60,
47 .range_num = 8,
48 },
49 { },
50};
Vignesh Raghavendra818c9392022-06-15 19:33:05 +0530[diff] [blame]51#endif /* CONFIG_SOC_K3_J721E */
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]52
Vignesh Raghavendra818c9392022-06-15 19:33:05 +0530[diff] [blame]53#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]54static struct ti_sci_resource_static_data rm_static_data[] = {
55 /* Free rings */
56 {
David Huang7bee6e12022-01-25 20:56:32 +0530[diff] [blame]57 .dev_id = 272,
58 .subtype = 1,
59 .range_start = 180,
60 .range_num = 32,
61 },
62 /* TX channels */
63 {
64 .dev_id = 273,
65 .subtype = 13,
66 .range_start = 12,
67 .range_num = 2,
68 },
69 /* RX channels */
70 {
71 .dev_id = 273,
72 .subtype = 10,
73 .range_start = 12,
74 .range_num = 2,
75 },
76 /* RX Free flows */
77 {
78 .dev_id = 273,
79 .subtype = 0,
80 .range_start = 80,
81 .range_num = 8,
82 },
83 { },
84};
Vignesh Raghavendra818c9392022-06-15 19:33:05 +0530[diff] [blame]85#endif /* CONFIG_SOC_K3_J721S2 */
David Huang7bee6e12022-01-25 20:56:32 +0530[diff] [blame]86
Bryan Brattlofa0659a52022-11-03 19:13:57 -0500[diff] [blame]87#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7)
Vignesh Raghavendra878fe832022-05-25 13:38:45 +0530[diff] [blame]88static struct ti_sci_resource_static_data rm_static_data[] = {
89 /* BC channels */
90 {
91 .dev_id = 26,
92 .subtype = 32,
93 .range_start = 18,
94 .range_num = 2,
95 },
96 { },
97};
Bryan Brattlofa0659a52022-11-03 19:13:57 -0500[diff] [blame]98#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
Vignesh Raghavendra878fe832022-05-25 13:38:45 +0530[diff] [blame]99
Apurva Nandan7a25c302024-02-24 01:51:45 +0530[diff] [blame]100#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
101static struct ti_sci_resource_static_data rm_static_data[] = {
102 /* Free rings */
103 {
104 .dev_id = 328,
105 .subtype = 1,
106 .range_start = 208,
107 .range_num = 32,
108 },
109 /* TX channels */
110 {
111 .dev_id = 329,
112 .subtype = 13,
113 .range_start = 40,
114 .range_num = 3,
115 },
116 /* RX channels */
117 {
118 .dev_id = 329,
119 .subtype = 10,
120 .range_start = 40,
121 .range_num = 3,
122 },
123 /* RX Free flows */
124 {
125 .dev_id = 329,
126 .subtype = 0,
127 .range_start = 84,
128 .range_num = 8,
129 },
130 { },
131};
132#endif /* CONFIG_SOC_K3_J784S4 */
133
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]134#else
135static struct ti_sci_resource_static_data rm_static_data[] = {
136 { },
137};
138#endif /* CONFIG_K3_DM_FW */
139#endif /* __TI_SCI_STATIC_DATA_H */