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git01.mediatek.com / filogic / uboot / 67c4f48a49bb428bca409b1f6b6ca03f448c3645 / . / board / mpc8260ads / mpc8260ads.c
blob: 1d920fe93430508d4cf1b990e3b8ed785124347c [file] [log] [blame]
wdenk67c4f482002-08-26 22:23:10 +0000[diff] [blame^]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
8 *
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
32#include <ioports.h>
33#include <mpc8260.h>
34
35/*
36 * I/O Port configuration table
37 *
38 * if conf is 1, then that port pin will be configured at boot time
39 * according to the five values podr/pdir/ppar/psor/pdat for that entry
40 */
41
42const iop_conf_t iop_conf_tab[4][32] = {
43
44 /* Port A configuration */
45 { /* conf ppar psor pdir podr pdat */
46 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
47 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
48 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
49 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
50 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
51 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
52 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
53 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
54 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
55 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
56 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
57 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
58 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
59 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
60 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
61 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
62 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
63 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
64 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
65 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
66 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
67 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
68 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
69 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
70 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
71 /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
72 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
73 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
74 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
75 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
76 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
77 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
78 },
79
80 /* Port B configuration */
81 { /* conf ppar psor pdir podr pdat */
82 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
83 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
84 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
85 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
86 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
87 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
88 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
89 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
90 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
91 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
92 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
93 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
94 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
95 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
96 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
97 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
98 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
99 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
100 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
101 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
102 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
103 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
104 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
105 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
106 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
107 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
108 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
109 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
110 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
111 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
112 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
113 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
114 },
115
116 /* Port C */
117 { /* conf ppar psor pdir podr pdat */
118 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
119 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
120 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
121 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
122 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
123 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
124 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
125 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
126 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
127 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
128 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
129 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
130 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
131 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
132 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
133 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
134 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
135 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
136 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
137 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
138 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
139 /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */
140 /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
141 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
142 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
143 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
144 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
145 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
146 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
147 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
148 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
149 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
150 },
151
152 /* Port D */
153 { /* conf ppar psor pdir podr pdat */
154 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
155 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
156 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
157 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
158 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
159 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
160 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
161 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
162 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
163 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
164 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
165 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
166 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
167 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
168 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
169 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
170 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
171 /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* LED */
172 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
173 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
174 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
175 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
176 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
177 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
178 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
179 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
180 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
181 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
182 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
183 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
184 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
185 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
186 }
187};
188
189typedef struct bscr_ {
190 unsigned long bcsr0;
191 unsigned long bcsr1;
192 unsigned long bcsr2;
193 unsigned long bcsr3;
194 unsigned long bcsr4;
195 unsigned long bcsr5;
196 unsigned long bcsr6;
197 unsigned long bcsr7;
198} bcsr_t;
199
200void reset_phy(void)
201{
202 volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
203
204 /* reset the FEC port */
205 bcsr->bcsr1 &= ~FETH_RST;
206 bcsr->bcsr1 |= FETH_RST;
207}
208
209
210int board_pre_init (void)
211{
212 volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
213 bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;
214
215 return 0;
216}
217
218long int initdram(int board_type)
219{
220 volatile immap_t *immap = (immap_t *)CFG_IMMR;
221 volatile memctl8260_t *memctl = &immap->im_memctl;
222 volatile uchar *ramaddr,
223 c = 0xff;
224 int i;
225
226#ifndef CFG_RAMBOOT
227 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
228 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
229 immap->im_siu_conf.sc_tescr1 = 0x00004000;
230
231 /* init local sdram, bank 4 */
232 memctl->memc_lsrt = 0x00000010;
233 memctl->memc_or4 = 0xFFC01480;
234 memctl->memc_br4 = 0x04001861;
235 memctl->memc_lsdmr = 0x2886A522;
236 ramaddr = (uchar *)CFG_LSDRAM_BASE;
237 *ramaddr = c;
238 memctl->memc_lsdmr = 0x0886A522;
239 for( i = 0; i < 8; i++ ) {
240 *ramaddr = c;
241 }
242 memctl->memc_lsdmr = 0x1886A522;
243 *ramaddr = c;
244 memctl->memc_lsdmr = 0x4086A522;
245
246 /* init sdram dimm */
247 ramaddr = (uchar *)CFG_SDRAM_BASE;
248 memctl->memc_psrt = 0x00000010;
249 immap->im_memctl.memc_or2 = 0xFF000CA0;
250 immap->im_memctl.memc_br2 = 0x00000041;
251 memctl->memc_psdmr = 0x296EB452;
252 *ramaddr = c;
253 memctl->memc_psdmr = 0x096EB452;
254 for (i = 0; i < 8; i++)
255 *ramaddr = c;
256
257 memctl->memc_psdmr = 0x196EB452;
258 *ramaddr = c;
259 memctl->memc_psdmr = 0x416EB452;
260 *ramaddr = c;
261#endif
262
263 /* return total ram size of simm */
264 return (16 * 1024 * 1024);
265}
266
267int checkboard(void)
268{
269 puts ("Board: Motorola MPC8260ADS\n");
270 return 0;
271}
272