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git01.mediatek.com / filogic / uboot / 67b6a8c731485414952b2ce9e22786574a0f9c46 / . / cpu / microblaze / irq.S
blob: 393d6e8dd42a32950174b6980ae510977cfb874a [file] [log] [blame]
Michal Simek952d5142007-03-11 13:42:58 +0100[diff] [blame]1/*
2 * (C) Copyright 2007 Michal Simek
3 *
4 * Michal SIMEK <monstr@monstr.eu>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26 .text
27 .global _interrupt_handler
28_interrupt_handler:
29 addi r1, r1, -4
30 swi r2, r1, 0
31 addi r1, r1, -4
32 swi r3, r1, 0
33 addi r1, r1, -4
34 swi r4, r1, 0
35 addi r1, r1, -4
36 swi r5, r1, 0
37 addi r1, r1, -4
38 swi r6, r1, 0
39 addi r1, r1, -4
40 swi r7, r1, 0
41 addi r1, r1, -4
42 swi r8, r1, 0
43 addi r1, r1, -4
44 swi r9, r1, 0
45 addi r1, r1, -4
46 swi r10, r1, 0
47 addi r1, r1, -4
48 swi r11, r1, 0
49 addi r1, r1, -4
50 swi r12, r1, 0
51 addi r1, r1, -4
52 swi r13, r1, 0
53 addi r1, r1, -4
54 swi r14, r1, 0
55 addi r1, r1, -4
56 swi r15, r1, 0
57 addi r1, r1, -4
58 swi r16, r1, 0
59 addi r1, r1, -4
60 swi r17, r1, 0
61 addi r1, r1, -4
62 swi r18, r1, 0
63 addi r1, r1, -4
64 swi r19, r1, 0
65 addi r1, r1, -4
66 swi r20, r1, 0
67 addi r1, r1, -4
68 swi r21, r1, 0
69 addi r1, r1, -4
70 swi r22, r1, 0
71 addi r1, r1, -4
72 swi r23, r1, 0
73 addi r1, r1, -4
74 swi r24, r1, 0
75 addi r1, r1, -4
76 swi r25, r1, 0
77 addi r1, r1, -4
78 swi r26, r1, 0
79 addi r1, r1, -4
80 swi r27, r1, 0
81 addi r1, r1, -4
82 swi r28, r1, 0
83 addi r1, r1, -4
84 swi r29, r1, 0
85 addi r1, r1, -4
86 swi r30, r1, 0
87 addi r1, r1, -4
88 swi r31, r1, 0
89 brlid r15, interrupt_handler
90 nop
91 nop
92 lwi r31, r1, 0
93 addi r1, r1, 4
94 lwi r30, r1, 0
95 addi r1, r1, 4
96 lwi r29, r1, 0
97 addi r1, r1, 4
98 lwi r28, r1, 0
99 addi r1, r1, 4
100 lwi r27, r1, 0
101 addi r1, r1, 4
102 lwi r26, r1, 0
103 addi r1, r1, 4
104 lwi r25, r1, 0
105 addi r1, r1, 4
106 lwi r24, r1, 0
107 addi r1, r1, 4
108 lwi r23, r1, 0
109 addi r1, r1, 4
110 lwi r22, r1, 0
111 addi r1, r1, 4
112 lwi r21, r1, 0
113 addi r1, r1, 4
114 lwi r20, r1, 0
115 addi r1, r1, 4
116 lwi r19, r1, 0
117 addi r1, r1, 4
118 lwi r18, r1, 0
119 addi r1, r1, 4
120 lwi r17, r1, 0
121 addi r1, r1, 4
122 lwi r16, r1, 0
123 addi r1, r1, 4
124 lwi r15, r1, 0
125 addi r1, r1, 4
126 lwi r14, r1, 0
127 addi r1, r1, 4
128 lwi r13, r1, 0
129 addi r1, r1, 4
130 lwi r12, r1, 0
131 addi r1, r1, 4
132 lwi r11, r1, 0
133 addi r1, r1, 4
134 lwi r10, r1, 0
135 addi r1, r1, 4
136 lwi r9, r1, 0
137 addi r1, r1, 4
138 lwi r8, r1, 0
139 addi r1, r1, 4
140 lwi r7, r1, 0
141 addi r1, r1, 4
142 lwi r6, r1, 0
143 addi r1, r1, 4
144 lwi r5, r1, 0
145 addi r1, r1, 4
146 lwi r4, r1, 0
147 addi r1, r1, 4
148 lwi r3, r1, 0
149 addi r1, r1, 4
150 lwi r2, r1, 0
151 addi r1, r1, 4
152
153 /* enable_interrupt */
Michal Simek67b6a8c2007-05-07 19:30:12 +0200[diff] [blame^]154 msrset r0, 2
Michal Simek952d5142007-03-11 13:42:58 +0100[diff] [blame]155 bra r14
156 nop
157 nop
158 .size _interrupt_handler,.-_interrupt_handler