blob: 44a3e7adf206149d06ef3e53104356a337c6087b [file] [log] [blame]
Andy Yanb5e16302019-11-14 11:21:12 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_RK3308_COMMON_H
7#define __CONFIG_RK3308_COMMON_H
8
9#include "rockchip-common.h"
10
11#define CONFIG_SYS_CBSIZE 1024
Andy Yanb5e16302019-11-14 11:21:12 +080012#define CONFIG_SPL_MAX_SIZE 0x20000
13#define CONFIG_SPL_BSS_START_ADDR 0x00400000
14#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
Andy Yanb5e16302019-11-14 11:21:12 +080015
16#define CONFIG_SYS_NS16550_MEM32
17
Andy Yanb5e16302019-11-14 11:21:12 +080018#define CONFIG_IRAM_BASE 0xfff80000
19#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
Andy Yanb5e16302019-11-14 11:21:12 +080020#define CONFIG_SPL_STACK 0x00400000
21#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
22
Andy Yanb5e16302019-11-14 11:21:12 +080023
24#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
25
26#define CONFIG_SYS_SDRAM_BASE 0
27#define SDRAM_MAX_SIZE 0xff000000
28#define SDRAM_BANK_SIZE (2UL << 30)
29
30#ifndef CONFIG_SPL_BUILD
31
32#define ENV_MEM_LAYOUT_SETTINGS \
33 "scriptaddr=0x00500000\0" \
34 "pxefile_addr_r=0x00600000\0" \
Andy Yan038626e2019-12-26 15:20:04 +080035 "fdt_addr_r=0x02800000\0" \
Andy Yanb5e16302019-11-14 11:21:12 +080036 "kernel_addr_r=0x00680000\0" \
37 "ramdisk_addr_r=0x04000000\0"
38
39#include <config_distro_bootcmd.h>
40#define CONFIG_EXTRA_ENV_SETTINGS \
41 ENV_MEM_LAYOUT_SETTINGS \
42 "partitions=" PARTS_DEFAULT \
43 ROCKCHIP_DEVICE_SETTINGS \
44 BOOTENV
45
46#endif
47
48#endif