Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 |
Vladimir Oltean | 5041e42 | 2021-09-17 14:27:13 +0300 | [diff] [blame] | 2 | * Copyright 2016-2019 NXP |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 3 | * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> |
| 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_H |
| 7 | #define __CONFIG_H |
| 8 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 9 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR |
| 10 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE |
| 11 | |
| 12 | /* XHCI Support - enabled by default */ |
| 13 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| 14 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 15 | #define DDR_SDRAM_CFG 0x470c0008 |
| 16 | #define DDR_CS0_BNDS 0x008000bf |
| 17 | #define DDR_CS0_CONFIG 0x80014302 |
| 18 | #define DDR_TIMING_CFG_0 0x50550004 |
| 19 | #define DDR_TIMING_CFG_1 0xbcb38c56 |
| 20 | #define DDR_TIMING_CFG_2 0x0040d120 |
| 21 | #define DDR_TIMING_CFG_3 0x010e1000 |
| 22 | #define DDR_TIMING_CFG_4 0x00000001 |
| 23 | #define DDR_TIMING_CFG_5 0x03401400 |
| 24 | #define DDR_SDRAM_CFG_2 0x00401010 |
| 25 | #define DDR_SDRAM_MODE 0x00061c60 |
| 26 | #define DDR_SDRAM_MODE_2 0x00180000 |
| 27 | #define DDR_SDRAM_INTERVAL 0x18600618 |
| 28 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 |
| 29 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 |
| 30 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 |
| 31 | #define DDR_DDR_CDR1 0x80040000 |
| 32 | #define DDR_DDR_CDR2 0x00000001 |
| 33 | #define DDR_SDRAM_CLK_CNTL 0x02000000 |
| 34 | #define DDR_DDR_ZQ_CNTL 0x89080600 |
| 35 | #define DDR_CS0_CONFIG_2 0 |
| 36 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 |
| 37 | #define SDRAM_CFG2_D_INIT 0x00000010 |
| 38 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 |
| 39 | #define SDRAM_CFG2_FRC_SR 0x80000000 |
| 40 | #define SDRAM_CFG_BI 0x00000001 |
| 41 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 42 | #ifdef CONFIG_SD_BOOT |
Tom Rini | 7cf9ab7 | 2020-06-16 19:06:25 -0400 | [diff] [blame] | 43 | #ifdef CONFIG_NXP_ESBC |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 44 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
Tom Rini | 7cf9ab7 | 2020-06-16 19:06:25 -0400 | [diff] [blame] | 45 | #endif /* ifdef CONFIG_NXP_ESBC */ |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 46 | |
| 47 | #define CONFIG_SPL_MAX_SIZE 0x1a000 |
| 48 | #define CONFIG_SPL_STACK 0x1001d000 |
| 49 | #define CONFIG_SPL_PAD_TO 0x1c000 |
| 50 | |
| 51 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
| 52 | CONFIG_SYS_MONITOR_LEN) |
| 53 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 54 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
| 55 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 56 | |
| 57 | #ifdef CONFIG_U_BOOT_HDR_SIZE |
| 58 | /* |
| 59 | * HDR would be appended at end of image and copied to DDR along |
| 60 | * with U-Boot image. Here u-boot max. size is 512K. So if binary |
| 61 | * size increases then increase this size in case of secure boot as |
| 62 | * it uses raw U-Boot image instead of FIT image. |
| 63 | */ |
| 64 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) |
| 65 | #else |
| 66 | #define CONFIG_SYS_MONITOR_LEN 0x100000 |
| 67 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
| 68 | #endif |
| 69 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 70 | #define PHYS_SDRAM 0x80000000 |
| 71 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) |
| 72 | |
| 73 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
| 74 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 75 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 76 | /* Serial Port */ |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 77 | #define CONFIG_SYS_NS16550_SERIAL |
| 78 | #ifndef CONFIG_DM_SERIAL |
| 79 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 80 | #endif |
| 81 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| 82 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 83 | /* I2C */ |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 84 | |
| 85 | /* EEPROM */ |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 86 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 87 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 88 | |
| 89 | /* QSPI */ |
| 90 | #define FSL_QSPI_FLASH_SIZE (1 << 24) |
| 91 | #define FSL_QSPI_FLASH_NUM 2 |
| 92 | |
| 93 | /* PCIe */ |
| 94 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 95 | #define CONFIG_PCIE2 /* PCIE controller 2 */ |
| 96 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" |
| 97 | #ifdef CONFIG_PCI |
| 98 | #define CONFIG_PCI_SCAN_SHOW |
| 99 | #endif |
| 100 | |
| 101 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 102 | |
| 103 | #define CONFIG_HWCONFIG |
| 104 | #define HWCONFIG_BUFFER_SIZE 256 |
| 105 | |
| 106 | #define CONFIG_FSL_DEVICE_DISABLE |
| 107 | |
| 108 | #define BOOT_TARGET_DEVICES(func) \ |
| 109 | func(MMC, mmc, 0) \ |
| 110 | func(USB, usb, 0) \ |
| 111 | func(DHCP, dhcp, na) |
| 112 | #include <config_distro_bootcmd.h> |
| 113 | |
| 114 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 115 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ |
| 116 | "initrd_high=0xffffffff\0" \ |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 117 | "kernel_addr=0x61000000\0" \ |
| 118 | "kernelheader_addr=0x60800000\0" \ |
| 119 | "scriptaddr=0x80000000\0" \ |
| 120 | "scripthdraddr=0x80080000\0" \ |
| 121 | "fdtheader_addr_r=0x80100000\0" \ |
| 122 | "kernelheader_addr_r=0x80200000\0" \ |
| 123 | "kernel_addr_r=0x80008000\0" \ |
| 124 | "kernelheader_size=0x40000\0" \ |
| 125 | "fdt_addr_r=0x8f000000\0" \ |
| 126 | "ramdisk_addr_r=0xa0000000\0" \ |
| 127 | "load_addr=0x80008000\0" \ |
| 128 | "kernel_size=0x2800000\0" \ |
| 129 | "kernel_addr_sd=0x8000\0" \ |
| 130 | "kernel_size_sd=0x14000\0" \ |
| 131 | "kernelhdr_addr_sd=0x4000\0" \ |
| 132 | "kernelhdr_size_sd=0x10\0" \ |
| 133 | BOOTENV \ |
| 134 | "boot_scripts=ls1021atsn_boot.scr\0" \ |
| 135 | "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \ |
| 136 | "scan_dev_for_boot_part=" \ |
| 137 | "part list ${devtype} ${devnum} devplist; " \ |
| 138 | "env exists devplist || setenv devplist 1; " \ |
| 139 | "for distro_bootpart in ${devplist}; do " \ |
| 140 | "if fstype ${devtype} " \ |
| 141 | "${devnum}:${distro_bootpart} " \ |
| 142 | "bootfstype; then " \ |
| 143 | "run scan_dev_for_boot; " \ |
| 144 | "fi; " \ |
| 145 | "done\0" \ |
| 146 | "scan_dev_for_boot=" \ |
| 147 | "echo Scanning ${devtype} " \ |
| 148 | "${devnum}:${distro_bootpart}...; " \ |
| 149 | "for prefix in ${boot_prefixes}; do " \ |
| 150 | "run scan_dev_for_scripts; " \ |
| 151 | "run scan_dev_for_extlinux; " \ |
| 152 | "done;" \ |
| 153 | "\0" \ |
| 154 | "boot_a_script=" \ |
| 155 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 156 | "${scriptaddr} ${prefix}${script}; " \ |
| 157 | "env exists secureboot && load ${devtype} " \ |
| 158 | "${devnum}:${distro_bootpart} " \ |
| 159 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ |
| 160 | "&& esbc_validate ${scripthdraddr};" \ |
| 161 | "source ${scriptaddr}\0" \ |
| 162 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 163 | "sf probe && sf read $load_addr " \ |
| 164 | "$kernel_addr $kernel_size; env exists secureboot " \ |
| 165 | "&& sf read $kernelheader_addr_r $kernelheader_addr " \ |
| 166 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 167 | "bootm $load_addr#$board\0" \ |
| 168 | "sd_bootcmd=echo Trying load from SD ..;" \ |
| 169 | "mmcinfo && mmc read $load_addr " \ |
| 170 | "$kernel_addr_sd $kernel_size_sd && " \ |
| 171 | "env exists secureboot && mmc read $kernelheader_addr_r " \ |
| 172 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ |
| 173 | " && esbc_validate ${kernelheader_addr_r};" \ |
| 174 | "bootm $load_addr#$board\0" |
| 175 | |
| 176 | /* Miscellaneous configurable options */ |
Alison Wang | 7147706 | 2020-02-03 15:25:19 +0800 | [diff] [blame] | 177 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
| 178 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 179 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 180 | #define CONFIG_SYS_PBSIZE \ |
| 181 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 182 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 183 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 184 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 185 | #define CONFIG_LS102XA_STREAM_ID |
| 186 | |
| 187 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 188 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 189 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 190 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 191 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 192 | /* Environment */ |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 193 | |
Jianchao Wang | e5332ba | 2019-07-19 00:30:01 +0300 | [diff] [blame] | 194 | #define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ |
| 195 | |
| 196 | #endif |