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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
maxims@google.com899b40f2017-01-18 13:44:57 -08002/*
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 * Ryan Chen <ryan_chen@aspeedtech.com>
5 *
6 * Copyright 2016 IBM Corporation
7 * (C) Copyright 2016 Google, Inc
maxims@google.com899b40f2017-01-18 13:44:57 -08008 */
9
Chia-Wei, Wang17cacab2020-08-03 17:36:08 +080010#ifndef _ASPEED_COMMON_CONFIG_H
11#define _ASPEED_COMMON_CONFIG_H
12
13#include <asm/arch/platform.h>
maxims@google.com899b40f2017-01-18 13:44:57 -080014
15/* Misc CPU related */
maxims@google.com899b40f2017-01-18 13:44:57 -080016
Chia-Wei, Wang17cacab2020-08-03 17:36:08 +080017#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
maxims@google.com899b40f2017-01-18 13:44:57 -080018
19#ifdef CONFIG_PRE_CON_BUF_SZ
Chia-Wei, Wang17cacab2020-08-03 17:36:08 +080020#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
21#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
maxims@google.com899b40f2017-01-18 13:44:57 -080022#else
Chia-Wei, Wang17cacab2020-08-03 17:36:08 +080023#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
24#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
maxims@google.com899b40f2017-01-18 13:44:57 -080025#endif
26
27#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
28 + CONFIG_SYS_INIT_RAM_SIZE)
29#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
30 - GENERATED_GBL_DATA_SIZE)
31
maxims@google.com899b40f2017-01-18 13:44:57 -080032/*
33 * NS16550 Configuration
34 */
maxims@google.com899b40f2017-01-18 13:44:57 -080035
maxims@google.com899b40f2017-01-18 13:44:57 -080036#endif /* __AST_COMMON_CONFIG_H */