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Thomas Choufb798b12015-10-09 13:46:34 +08001menu "Timer Support"
2
3config TIMER
Bin Meng8a7b8642015-11-13 00:11:14 -08004 bool "Enable driver model for timer drivers"
Thomas Choufb798b12015-10-09 13:46:34 +08005 depends on DM
6 help
Bin Meng8a7b8642015-11-13 00:11:14 -08007 Enable driver model for timer access. It uses the same API as
8 lib/time.c, but now implemented by the uclass. The first timer
Thomas Choufb798b12015-10-09 13:46:34 +08009 will be used. The timer is usually a 32 bits free-running up
10 counter. There may be no real tick, and no timer interrupt.
11
Philipp Tomsich4fac4ea2017-07-28 17:38:42 +020012config SPL_TIMER
13 bool "Enable driver model for timer drivers in SPL"
14 depends on TIMER && SPL
15 help
16 Enable support for timer drivers in SPL. These can be used to get
17 a timer value when in SPL, or perhaps for implementing a delay
18 function. This enables the drivers in drivers/timer as part of an
19 SPL build.
20
21config TPL_TIMER
22 bool "Enable driver model for timer drivers in TPL"
23 depends on TIMER && TPL
24 help
25 Enable support for timer drivers in TPL. These can be used to get
26 a timer value when in TPL, or perhaps for implementing a delay
27 function. This enables the drivers in drivers/timer as part of an
28 TPL build.
29
Simon Glass32f6c172016-02-24 09:14:49 -070030config TIMER_EARLY
31 bool "Allow timer to be used early in U-Boot"
32 depends on TIMER
Simon Glass6abd89b2018-09-02 17:02:24 -060033 # initr_bootstage() requires a timer and is called before initr_dm()
34 # so only the early timer is available
35 default y if X86 && BOOTSTAGE
Simon Glass32f6c172016-02-24 09:14:49 -070036 help
37 In some cases the timer must be accessible before driver model is
38 active. Examples include when using CONFIG_TRACE to trace U-Boot's
39 execution before driver model is set up. Enable this option to
40 use an early timer. These functions must be supported by your timer
41 driver: timer_early_get_count() and timer_early_get_rate().
42
Bin Meng19f88b22018-10-10 22:07:02 -070043config AG101P_TIMER
44 bool "AG101P timer support"
45 depends on TIMER && NDS32
46 help
47 Select this to enable a timer for AG01P devices.
48
Thomas Chou221d2ac2015-10-22 22:28:53 +080049config ALTERA_TIMER
Bin Meng8a7b8642015-11-13 00:11:14 -080050 bool "Altera timer support"
Thomas Chou221d2ac2015-10-22 22:28:53 +080051 depends on TIMER
52 help
Bin Meng8a7b8642015-11-13 00:11:14 -080053 Select this to enable a timer for Altera devices. Please find
Thomas Chou221d2ac2015-10-22 22:28:53 +080054 details on the "Embedded Peripherals IP User Guide" of Altera.
55
Sean Anderson5a238652020-10-25 21:46:57 -040056config ANDES_PLMT_TIMER
Sean Anderson5abf1f32020-10-25 21:46:56 -040057 bool
58 depends on RISCV_MMODE || SPL_RISCV_MMODE
59 help
60 The Andes PLMT block holds memory-mapped mtime register
61 associated with timer tick.
62
Bin Meng19f88b22018-10-10 22:07:02 -070063config ARC_TIMER
64 bool "ARC timer support"
65 depends on TIMER && ARC && CLK
66 help
67 Select this to enable built-in ARC timers.
68 ARC cores may have up to 2 built-in timers: timer0 and timer1,
69 usually at least one of them exists. Either of them is supported
70 in U-Boot.
71
72config AST_TIMER
73 bool "Aspeed ast2400/ast2500 timer support"
74 depends on TIMER
75 default y if ARCH_ASPEED
76 help
77 Select this to enable timer for Aspeed ast2400/ast2500 devices.
78 This is a simple sys timer driver, it is compatible with lib/time.c,
79 but does not support any interrupts. Even though SoC has 8 hardware
80 counters, they are all treated as a single device by this driver.
81 This is mostly because they all share several registers which
82 makes it difficult to completely separate them.
83
84config ATCPIT100_TIMER
85 bool "ATCPIT100 timer support"
86 depends on TIMER
87 help
88 Select this to enable a ATCPIT100 timer which will be embedded
89 in AE3XX, AE250 boards.
90
Wenyou.Yang@microchip.comce8a36f2017-08-15 17:40:26 +080091config ATMEL_PIT_TIMER
92 bool "Atmel periodic interval timer support"
93 depends on TIMER
94 help
95 Select this to enable a periodic interval timer for Atmel devices,
96 it is designed to offer maximum accuracy and efficient management,
97 even for systems with long response time.
98
Clément Léger7e5c11b2022-03-31 10:55:06 +020099config ATMEL_TCB_TIMER
100 bool "Atmel timer counter support"
101 depends on TIMER
102 depends on ARCH_AT91
103 help
104 Select this to enable the use of the timer counter as a monotonic
105 counter.
106
Michal Simekc3caac52018-04-17 13:40:46 +0200107config CADENCE_TTC_TIMER
108 bool "Cadence TTC (Triple Timer Counter)"
109 depends on TIMER
110 help
111 Enables support for the cadence ttc driver. This driver is present
112 on Xilinx Zynq and ZynqMP SoCs.
113
Marek Vasut442c0f12018-08-18 15:58:32 +0200114config DESIGNWARE_APB_TIMER
115 bool "Designware APB Timer"
116 depends on TIMER
117 help
118 Enables support for the Designware APB Timer driver. This timer is
119 present on Altera SoCFPGA SoCs.
120
Bin Meng19f88b22018-10-10 22:07:02 -0700121config MPC83XX_TIMER
122 bool "MPC83xx timer support"
123 depends on TIMER
Bin Mengb2aa4c52015-11-13 00:11:24 -0800124 help
Bin Meng19f88b22018-10-10 22:07:02 -0700125 Select this to enable support for the timer found on
126 devices based on the MPC83xx family of SoCs.
Bin Mengb2aa4c52015-11-13 00:11:24 -0800127
Marek Vasut6be61c62019-05-04 17:30:58 +0200128config RENESAS_OSTM_TIMER
129 bool "Renesas RZ/A1 R7S72100 OSTM Timer"
130 depends on TIMER
131 help
132 Enables support for the Renesas OSTM Timer driver.
133 This timer is present on Renesas RZ/A1 R7S72100 SoCs.
134
Bin Meng917d2b82021-07-28 12:00:22 +0800135config X86_TSC_TIMER_FREQ
136 int "x86 TSC timer frequency in Hz"
Bin Meng855e6572018-10-13 20:52:10 -0700137 depends on X86_TSC_TIMER
Bin Meng917d2b82021-07-28 12:00:22 +0800138 default 1000000000
Bin Meng855e6572018-10-13 20:52:10 -0700139 help
Bin Meng917d2b82021-07-28 12:00:22 +0800140 Sets the estimated CPU frequency in Hz when TSC is used as the
Bin Meng855e6572018-10-13 20:52:10 -0700141 early timer and the frequency can neither be calibrated via some
142 hardware ways, nor got from device tree at the time when device
143 tree is not available yet.
144
Stephan Gerhold7b0c1c52020-01-04 18:45:15 +0100145config NOMADIK_MTU_TIMER
146 bool "Nomadik MTU Timer"
147 depends on TIMER
148 help
149 Enables support for the Nomadik Multi Timer Unit (MTU),
150 used in ST-Ericsson Ux500 SoCs.
151 The MTU provides 4 decrementing free-running timers.
152 At the moment, only the first timer is used by the driver.
153
Mugunthan V Nafae3702015-12-24 16:08:07 +0530154config OMAP_TIMER
155 bool "Omap timer support"
156 depends on TIMER
157 help
158 Select this to enable an timer for Omap devices.
159
Bin Meng25399032018-12-12 06:12:27 -0800160config RISCV_TIMER
161 bool "RISC-V timer support"
162 depends on TIMER && RISCV
163 help
Sean Anderson9baaaef2020-09-28 10:52:21 -0400164 Select this to enable support for a generic RISC-V S-Mode timer
165 driver.
Bin Meng25399032018-12-12 06:12:27 -0800166
Bin Meng19f88b22018-10-10 22:07:02 -0700167config ROCKCHIP_TIMER
168 bool "Rockchip timer support"
maxims@google.comf57bd002017-01-18 13:44:55 -0800169 depends on TIMER
maxims@google.comf57bd002017-01-18 13:44:55 -0800170 help
Bin Meng19f88b22018-10-10 22:07:02 -0700171 Select this to enable support for the timer found on
172 Rockchip devices.
173
174config SANDBOX_TIMER
175 bool "Sandbox timer support"
176 depends on SANDBOX && TIMER
177 help
178 Select this to enable an emulated timer for sandbox. It gets
179 time from host os.
maxims@google.comf57bd002017-01-18 13:44:55 -0800180
Patrice Chotard200a7992017-02-21 13:37:05 +0100181config STI_TIMER
182 bool "STi timer support"
183 depends on TIMER
184 default y if ARCH_STI
185 help
186 Select this to enable a timer for STi devices.
187
Patrice Chotardfdfefdc2018-02-07 10:44:45 +0100188config STM32_TIMER
Bin Meng19f88b22018-10-10 22:07:02 -0700189 bool "STM32 timer support"
Patrice Chotardfdfefdc2018-02-07 10:44:45 +0100190 depends on TIMER
191 help
192 Select this to enable support for the timer found on
193 STM32 devices.
194
Bin Meng19f88b22018-10-10 22:07:02 -0700195config X86_TSC_TIMER
196 bool "x86 Time-Stamp Counter (TSC) timer support"
197 depends on TIMER && X86
Mario Six3c516552018-08-06 10:23:38 +0200198 help
Bin Meng19f88b22018-10-10 22:07:02 -0700199 Select this to enable Time-Stamp Counter (TSC) timer for x86.
Mario Six3c516552018-08-06 10:23:38 +0200200
Simon Glassd3edd422019-12-06 21:41:49 -0700201config X86_TSC_READ_BASE
202 bool "Read the TSC timer base on start-up"
203 depends on X86_TSC_TIMER
204 help
205 On x86 platforms the TSC timer tick starts at the value 0 on reset.
206 This it makes no sense to read the timer on boot and use that as the
207 base, since we will miss some time taken to load U-Boot, etc. This
208 delay is controlled by the SoC and we cannot reduce it, but for
209 bootstage we want to record the time since reset as accurately as
210 possible.
211
212 The only exception is when U-Boot is used as a secondary bootloader,
213 where this option should be enabled.
214
Simon Glassbba203e2019-12-06 21:41:50 -0700215config TPL_X86_TSC_TIMER_NATIVE
216 bool "x86 TSC timer uses native calibration"
217 depends on TPL && X86_TSC_TIMER
218 help
219 Selects native timer calibration for TPL and don't include the other
220 methods in the code. This helps to reduce code size in TPL and works
221 on fairly modern Intel chips. Code-size reductions is about 700
222 bytes.
223
developer4a347352018-11-15 10:07:56 +0800224config MTK_TIMER
225 bool "MediaTek timer support"
226 depends on TIMER
227 help
228 Select this to enable support for the timer found on
229 MediaTek devices.
230
Claudiu Beznea5669c3d2020-09-07 18:36:33 +0300231config MCHP_PIT64B_TIMER
232 bool "Microchip 64-bit periodic interval timer support"
233 depends on TIMER
234 help
235 Select this to enable support for Microchip 64-bit periodic
236 interval timer.
237
Giulio Benetti9aed42b2021-05-13 12:18:31 +0200238config IMX_GPT_TIMER
239 bool "NXP i.MX GPT timer support"
240 depends on TIMER
241 help
242 Select this to enable support for the timer found on
243 NXP i.MX devices.
244
Thomas Choufb798b12015-10-09 13:46:34 +0800245endmenu